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AMD Artix US+

AMD Artix US+

Non-hardware verified power tree for AMD Artix US+ FPGA designs.

AMD Artix US+ Power Tree (AU10P/15P)

Download Block Diagram

Please refer to the "Design Tools, Software and Chat AI" section of our Terms of Use.

Product SKU

Descripton

Synchronous buck regulator EN and PG. VIN from 2.3V to 5.5V, Vout from 0.3V to 2V, up to 3A load. 1.36x0.432mm WLCSP12

NCP59801CMLADJTCG

1A LDO, 1.2V VOUT, with Enable / Power Good WDFNW6_2x2mm

NCP189CMTW180TAG

500mA LDO, 1.8V VOUT, with Enable / Power Good. WDFNW6_2x2mm

synchronous buck regulator w/ Enable / Power Good. VIN from 2.9V to 5.5V up to 6A load. VOUT from 0.6V to 0.84 X VIN3x3mm QFN16

Source/sink Double Data Rate (DDR1, 2, 3) 3A termination regulator

AMD Artix US+ Power Tree (AU20P/25P)

Download Block Diagram

Please refer to the "Design Tools, Software and Chat AI" section of our Terms of Use.

Product SKU

Descripton

Synchronous buck regulator w/ Enable / Power Good. VIN from 2.9V to 5.5V up to 6A load. VOUT from 0.6 V to 0.84 X VIN3x3mm QFN16.

NCP59801CMLADJTCG

1A LDO, 1.2V VOUT, with Enable / Power Good WDFNW6_2x2mm

NCP189CMTW180TAG

500mA LDO, 1.8V VOUT, with Enable / Power Good. WDFNW6_2x2mm

Synchronous buck regulator EN and PG. VIN from 2.3V to 5.5V, Vout from 0.3V to 2V, up to 3A load. 1.36x0.432mm WLCSP12

Synchronous buck regulator w/ Enable / Power Good. VIN from 2.9V to 5.5V up to 5A load. VOUT from 0.6V to 0.84 X VIN3x3mm QFN16

Source/sink Double Data Rate (DDR1, 2, 3) 3A termination regulator