Pulse Counter
The pulse counter is used to observe an input signal and count the number of clock periods, during either of the following situations:
- A rising edge is observed
- The signal is at a high level
The pulse counter is an input to the ultra-low power data acquisition system (see Ultra-Low Power Data Acquisition Subsystem), and is clocked using the SENSOR_CLK defined by that block. The pulse counter is reset with the SAR-ADC when the SENSOR_CTRL_RESET bit in the SENSOR_CTRL register is set.
The pulse counter is configured using the SENSOR_PC_CFG register, as follows:
- Select between counting rising edges and high-level periods using the SENSOR_PC_CFG_PC_COUNT_ON bit.
- Select the input signal to the pulse counter from one of GPIO0 to GPIO4, or from a constant source, using the SENSOR_PC_CFG_PC_SRC_SEL bit field.
- Set the measurement duration of between 1 and 1023 cycles using the SENSOR_PC_CFG_COUNT_INT bit field.
The "Example counting using the pulse counter" figure shows how the pulse counter is updated in each mode based on an example input.
The current value of the pulse counter can be read through the SENSOR_PC_COUNT register, and the output from the pulse counter is captured using the ultra-low power data acquisition system's accumulator, FIFO, or threshold blocksUltra-Low Power Data Acquisition Subsystem
NOTE: If the pulse counter is clocked using the RTC (a clock which is not synchronous to SYSCLK), the current count read from the SENSOR_PC_COUNT register can be unstable. Therefore, to maintain data integrity, ensure that the data is read repeatedly until two consecutive reads match.
For registers, see Pulse Counter Registers.