Nested Vector Interrupt Controller (NVIC)
The Arm Cortex-M33 processor is closely tied to a nested vectored interrupt controller (NVIC), which is a private peripheral provided for the processor that supports interrupt and fault handling functionality. This block is implemented with the Arm Cortex-M33 processor and is described in the ARM Cortex-M33 Technical Reference Manual.
The Arm Cortex-M33 processor as implemented for RSL15 uses pulse interrupts. These interrupts are sampled on the rising edge of SYSCLK. A pulse interrupt can be reasserted during the ISR so that the interrupt can be in the pending state and active at the same time. If another pulse arrives while the interrupt is still pending, the interrupt remains pending and the ISR runs only once.
The NVIC handles a non-maskable interrupt (NMI), predefined interrupts, several faults, and a set of general-purpose interrupts that are external to the Arm Cortex-M33 processor and are linked to its interfaces and peripherals. A list of the interrupts supported by the NVIC for the Arm Cortex-M33 processor is provided in the "Interrupts in the Arm Cortex-M33 Processor" table
IMPORTANT: For best practices in error, fault, and watchdog interrupt handling see Diagnostic Strategies from the RSL15 Developer's Guide. |
Interrupt Priority Registers
Use the Interrupt Priority Registers (NVIC_IP*) to assign a priority to each of the available interrupts. Each byte in an Interrupt Priority can be used to set the priority for one of the external interrupts (vectors 16 to 72) listed in Interrupts in the Arm Cortex-M33 Processor (table).
NOTE: Configuration of the interrupt priorities for standard Arm Cortex-M33 processor exceptions (vectors 4 to 15) are set using the System Handler Priority registers. For more information, see the ARMv8M Architecture Reference Manual.
The NVIC for the Arm Cortex-M33 processor in the RSL15 system has been implemented with three interrupt priority bits per interrupt. These three priority bits are MSB aligned to an eight-bit priority bit field as required by Arm. Generally, the lower the priority value, the higher the priority that interrupt is given.
The interrupt priority settings are divided into interrupt priority groups, configured using the SCB_AIRCR register, with preemption in lower numbered groups with interrupts within a group sorted by interrupt priority settings and finally if required sorted by vector number. Interrupts can be further prioritized to deprioritize all non-secure interrupts when one or more secure interrupts are pending. When choosing which interrupt to activate, the priority settings are applied as follows:
- When multiple interrupts are pending, but no interrupts are active, the interrupt with the lowest priority setting is activated. If more than one pending interrupt shares the lowest priority setting, the interrupt with the lower vector number is activated.
- If an interrupt is currently active, it can be pre-empted by any interrupt that is pended in a lower numbered group. If multiple interrupts that could pre-empt the active interrupt are pending, the interrupt with the lowest priority setting is activated. As before, if more than one pending interrupt shares the lowest priority setting, the interrupt with the lower vector number is activated.
IMPORTANT: The reset, NMI and fault vectors have priority levels of -3, -2, and -1 respectively. As such, these events can always pre-empt interrupts with lower priorities. |
For this peripheral’s registers, see NVIC Registers.