Sensor Interface
Address |
Register Name |
Register Write |
Register Read |
Default |
Description |
---|---|---|---|---|---|
0x40001D00 |
SENSOR_SAR_CFG |
(22:20) SAR_PRE_SEL_ODD |
(22:20) SAR_PRE_SEL_ODD |
0x0 |
Pre-selection of odd GPIOs |
|
|
(18:16) SAR_PRE_SEL_EVEN |
(18:16) SAR_PRE_SEL_EVEN |
0x0 |
Pre-selection of even GPIOs |
|
|
(14:12) SAR_IN_P |
(14:12) SAR_IN_P |
0x4 |
Defines the positive input signal |
|
|
(10:8) SAR_IN_N |
(10:8) SAR_IN_N |
0x4 |
Defines the negative input signal |
|
|
(3) SAR_DATA_OUT_RX_DMA_EN |
(3) SAR_DATA_OUT_RX_DMA_EN |
0x0 |
Enable / disable the DMA trigger when SAR data available |
|
|
(2) SAR_DATA_OUT_UPDATE |
(2) SAR_DATA_OUT_UPDATE |
0x0 |
Enable / disable the SAR data update |
|
|
(1) SAR_SUPPLY_EN |
(1) SAR_SUPPLY_EN |
0x0 |
Enable / disable the SAR supply |
|
|
(0) SAR_SUPPLY_SELECT |
(0) SAR_SUPPLY_SELECT |
0x0 |
SAR supply selection |
0x40001D04 |
SENSOR_SAR_CTRL |
(14) START_SINGLE |
- |
N/A |
Start single conversion command |
|
|
(13) START_CONTINUOUS |
(13) START_CONTINUOUS |
0x0 |
Start continuous conversions command |
|
|
- |
(12) BUSY |
0x0 |
Conversion in progess flag |
|
|
(9:8) MODE |
(9:8) MODE |
0x0 |
Conversion mode selection |
|
|
(6:4) NUM_SAMPLE |
(6:4) NUM_SAMPLE |
0x0 |
Defines the number of clk cycles for data sampling |
|
|
(3:0) OUT_SEL |
(3:0) OUT_SEL |
0x0 |
Output selection (undefined values return 0) |
0x40001D08 |
SENSOR_SAR_DATA |
- |
(15:0) SAR_OUT |
0x0 |
15 bit SAR conversion result (signed) |
0x40001D0C |
SENSOR_PC_CFG |
(16) PC_COUNT_ON |
(16) PC_COUNT_ON |
0x0 |
Pulse counter count on rising edge or high state |
|
|
(14:12) PC_SRC_SEL |
(14:12) PC_SRC_SEL |
0x5 |
Pulse count source selection |
|
|
(9:0) COUNT_INT |
(9:0) COUNT_INT |
0x3 |
Duration of count state |
0x40001D10 |
SENSOR_PC_COUNT |
- |
(9:0) VALUE |
0x0 |
Sensor pulse counter current value |
0x40001D14 |
SENSOR_TIMER_COUNT |
- |
(9:0) VALUE |
0x0 |
Sensor timer counter current value |
0x40001D18 |
SENSOR_CFG |
(24) CLK_SEL |
(24) CLK_SEL |
0x1 |
Clock source selection |
|
|
(20) SRC_SEL |
(20) SRC_SEL |
0x0 |
Sample source selection |
|
|
(13) DLY_EN |
(13) DLY_EN |
0x1 |
Delay state enable |
|
|
(12) DLY_DIV_EN |
(12) DLY_DIV_EN |
0x0 |
Delay divider selection |
|
|
(9:0) DLY |
(9:0) DLY |
0x0 |
Absolute Value of main counter to trigger the change of delay state |
0x40001D1C |
SENSOR_CTRL |
(31) RESET |
- |
N/A |
Reset the Sensor interface (SAR and Pulse Counter) |
|
|
- |
(12) STATE |
0x0 |
Sensor state |
|
|
- |
(8) STATUS |
0x0 |
Sensor status |
|
|
(0) ENABLE |
(0) ENABLE |
0x0 |
Sensor |
0x40001D20 |
SENSOR_FIFO_CFG |
- |
(12:8) FIFO_LEVEL |
0x0 |
Number of samples stored in FIFO |
|
|
(6) FIFO_RX_INT_EN |
(6) FIFO_RX_INT_EN |
0x0 |
Enable / disable the interrupt when FIFO is full |
|
|
(5) FIFO_RX_DMA_EN |
(5) FIFO_RX_DMA_EN |
0x0 |
Enable / disable the DMA trigger when FIFIO is full |
|
|
(4) FIFO_STORE_EN |
(4) FIFO_STORE_EN |
0x1 |
Enable the storage of sample on the FIFO |
|
|
(3:0) FIFO_SIZE |
(3:0) FIFO_SIZE |
0x0 |
Number of samples stored before waking up the core |
0x40001D24 |
SENSOR_PROCESSING |
(24) SUM_EN |
(24) SUM_EN |
0x0 |
Summation enable |
|
|
(19:16) NBR_SAMPLES |
(19:16) NBR_SAMPLES |
0x0 |
Number of samples used for wakeup in sensor detect mode |
0x40001D28 |
SENSOR_THRESHOLD_MIN |
(23) THRESHOLD_MIN_EN |
(23) THRESHOLD_MIN_EN |
0x0 |
Threshold min comparator is enabled. |
|
|
(18:0) THRESHOLD_MIN |
(18:0) THRESHOLD_MIN |
0x0 |
Absolute sensor data threshold min for wake-up |
0x40001D2C |
SENSOR_THRESHOLD_MAX |
(23) THRESHOLD_MAX_EN |
(23) THRESHOLD_MAX_EN |
0x0 |
Threshold max comparator is enabled |
|
|
(18:0) THRESHOLD_MAX |
(18:0) THRESHOLD_MAX |
0x0 |
Absolute sensor data threshold max for wake-up |
0x40001D30 - 0x40001D6C |
SENSOR_FIFO_DATA_* |
- |
(31:0) VALUE |
0x0 |
Sensor FIFO output data (signed) |