System Control
Address |
Register Name |
Register Write |
Register Read |
Default |
Description |
---|---|---|---|---|---|
0x40000000 |
SYSCTRL_CM33_LOOP_CACHE_CFG |
(0) CM33_LOOP_CACHE_ENABLE |
(0) CM33_LOOP_CACHE_ENABLE |
0x0 |
CM33 loop cache enable |
0x40000004 |
SYSCTRL_ACCESS_ERROR |
(16) ACCESS_ERROR_CLEAR |
- |
N/A |
Write a 1 to clear the access error flags |
|
|
- |
(12) CC312_MEM_ERROR |
0x0 |
CC312 memory error flag |
|
|
- |
(10) DMA_PERIPH_ERROR |
0x0 |
DMA peripheral access error flag |
|
|
- |
(9) DMA_MEM_ERROR |
0x0 |
DMA memory error flag |
|
|
- |
(8) BB_MEM_ERROR |
0x0 |
Baseband memory error flag |
|
|
- |
(0) FLASH_COPIER_MEM_ERROR |
0x0 |
FLASH[0:0] copier memory error flag |
0x40000008 |
SYSCTRL_MEM_POWER_STARTUP |
(17:16) BB_DRAM_STARTUP |
(17:16) BB_DRAM_STARTUP |
0x3 |
Baseband DRAM[1:0] power startup control |
|
|
(15:8) DRAM_STARTUP |
(15:8) DRAM_STARTUP |
0xFF |
DRAM[7:0] power startup control |
|
|
(1) FLASH_STARTUP |
(1) FLASH_STARTUP |
0x0 |
Flash[0:0] power startup control |
|
|
(0) PROM_STARTUP |
(0) PROM_STARTUP |
0x1 |
PROM power startup control |
0x4000000C |
SYSCTRL_MEM_POWER_ENABLE |
(17:16) BB_DRAM_ENABLE |
(17:16) BB_DRAM_ENABLE |
0x0 |
Baseband DRAM[1:0] power enable control |
|
|
(15:8) DRAM_ENABLE |
(15:8) DRAM_ENABLE |
0x1 |
DRAM[7:0] power enable control |
|
|
(1) FLASH_ENABLE |
(1) FLASH_ENABLE |
0x0 |
Flash[0:0] power enable control |
|
|
(0) PROM_ENABLE |
(0) PROM_ENABLE |
0x1 |
PROM power enable control |
0x40000018 |
SYSCTRL_MEM_ACCESS_CFG |
(29:24) WAKEUP_ADDR_PACKED |
(29:24) WAKEUP_ADDR_PACKED |
0x0 |
Wakeup restore address in packed 6-bit format. When written, SYSCTRL_WAKEUP_ADDR is updated. This field reads back as zero when SYSCTRL_WAKEUP_ADDR does not point to an enabled RAM instance. |
|
|
(17:16) BB_DRAM_ACCESS |
(17:16) BB_DRAM_ACCESS |
0x0 |
Baseband DRAM[1:0] access configuration |
|
|
(15:8) DRAM_ACCESS |
(15:8) DRAM_ACCESS |
0x1 |
DRAM[7:0] access configuration |
|
|
(1) FLASH_ACCESS |
(1) FLASH_ACCESS |
0x0 |
FLASH[0:0] access configuration |
|
|
(0) PROM_ACCESS |
(0) PROM_ACCESS |
0x1 |
PROM access configuration |
0x4000001C |
SYSCTRL_WAKEUP_ADDR |
(31:0) WAKEUP_ADDR |
(31:0) WAKEUP_ADDR |
0x0 |
Wake-up restore address in unpacked 32-bit format. |
0x40000020 |
SYSCTRL_MEM_RETENTION_CFG |
(17:16) BB_DRAM_RETENTION |
(17:16) BB_DRAM_RETENTION |
0x3 |
Baseband DRAM[1:0] retention configuration |
|
|
(15:8) DRAM_RETENTION |
(15:8) DRAM_RETENTION |
0xFE |
DRAM[7:0] retention configuration |
0x40000024 |
SYSCTRL_MEM_TIMING_CFG |
(22:20) RAM_PKA_EMA |
(22:20) RAM_PKA_EMA |
0x2 |
RAM extra margin configuration for PKA RAM |
|
|
(17:16) RAM_PKA_EMAW |
(17:16) RAM_PKA_EMAW |
0x0 |
RAM write extra margin configuration for PKA RAM |
|
|
(6:4) PROM_EMA |
(6:4) PROM_EMA |
0x2 |
PROM extra margin configuration |
|
|
(0) PROM_KEN |
(0) PROM_KEN |
0x1 |
PROM bit lines keeper configuration |
0x40000028 |
SYSCTRL_RF_POWER_CFG |
(9) BB_ENABLE |
(9) BB_ENABLE |
0x0 |
Base Band power enable control |
|
|
(8) BB_STARTUP |
(8) BB_STARTUP |
0x0 |
Base Band power startup control |
|
|
(1) RF_ENABLE |
(1) RF_ENABLE |
0x0 |
RF power enable control |
|
|
(0) RF_STARTUP |
(0) RF_STARTUP |
0x0 |
RF power startup control |
0x4000002C |
SYSCTRL_RF_ACCESS_CFG |
(8) BB_ACCESS |
(8) BB_ACCESS |
0x0 |
Base Band access |
|
|
(1) RF_IRQ_ACCESS |
(1) RF_IRQ_ACCESS |
0x0 |
RF IRQ access configuration |
|
|
(0) RF_ACCESS |
(0) RF_ACCESS |
0x0 |
RF access configuration |
0x40000038 |
SYSCTRL_FPU_PWR_CFG |
(31:16) FPU_PWR_KEY |
- |
N/A |
Key to enable write to this register |
|
|
(10) PWRUP_FPU_TRICKLE |
(10) PWRUP_FPU_TRICKLE |
0x1 |
Power control for FPU primary current in-rush limited supply |
|
|
(9) PWRUP_FPU_HAMMER |
(9) PWRUP_FPU_HAMMER |
0x1 |
Power control for FPU primary low impedance supply |
|
|
(8) ISOLATE_FPU |
(8) ISOLATE_FPU |
0x0 |
Isolation control for FPU |
|
|
(3) FPU_Q_REQ |
(3) FPU_Q_REQ |
0x0 |
FPU domain quiescence request signal |
|
|
- |
(2) FPU_Q_ACCEPT |
0x0 |
FPU domain quiescence request accepted |
|
|
- |
(1) FPU_Q_DENY |
0x0 |
FPU domain quiescence request denied |
|
|
- |
(0) FPU_Q_ACTIVE |
0x1 |
FPU logic active or activation request |
0x4000003C |
SYSCTRL_DBG_PWR_CFG |
(31:16) DBG_PWR_KEY |
- |
N/A |
Key to enable write to this register |
|
|
(10) PWRUP_DBG_TRICKLE |
(10) PWRUP_DBG_TRICKLE |
0x1 |
Power control for Debug primary current in-rush limited supply |
|
|
(9) PWRUP_DBG_HAMMER |
(9) PWRUP_DBG_HAMMER |
0x1 |
Power control for Debug primary low impedance supply |
|
|
(8) ISOLATE_DBG |
(8) ISOLATE_DBG |
0x0 |
Isolation control for Debug |
|
|
(3) DBG_Q_REQ |
(3) DBG_Q_REQ |
0x0 |
Debug domain quiescence request signal |
|
|
- |
(2) DBG_Q_ACCEPT |
0x0 |
Debug domain quiescence request accepted |
|
|
- |
(1) DBG_Q_DENY |
0x0 |
Debug domain quiescence request denied |
|
|
- |
(0) DBG_Q_ACTIVE |
0x0 |
Debug logic active or activation request |
0x40000040 |
SYSCTRL_CRYPTOCELL_PWR_CFG |
(31:16) PWR_KEY |
- |
N/A |
Key to enable write to this register |
|
|
- |
(4) CC_CG_STATE |
0x0 |
CryptoCell central clock gating state |
|
|
(3) CC_POWER_STARTUP |
(3) CC_POWER_STARTUP |
0x0 |
Power control for CryptoCell |
|
|
(2) CC_POWER_ENABLE |
(2) CC_POWER_ENABLE |
0x0 |
Power control for CryptoCell |
|
|
(1) CC_ISOLATE_N |
(1) CC_ISOLATE_N |
0x0 |
CryptoCell isolate control signal |
|
|
- |
(0) CC_POWERDOWN_RDY |
0x0 |
Indicates that CryptoCell can be powered down |
0x40000044 |
SYSCTRL_NS_ACCESS_PERIPH_CFG0 |
(28) PWM_ACCESS |
(28) PWM_ACCESS |
0x0 |
Allow Non-Secure code to access the PWM |
|
|
(27) LIN_ACCESS |
(27) LIN_ACCESS |
0x0 |
Allow Non-Secure code to access the LIN[0:0] |
|
|
(26) TOF_ACCESS |
(26) TOF_ACCESS |
0x0 |
Allow Non-Secure code to access the TOF |
|
|
(25) PCM_ACCESS |
(25) PCM_ACCESS |
0x0 |
Allow Non-Secure code to access the PCM[0:0] |
|
|
(24) UART_ACCESS |
(24) UART_ACCESS |
0x0 |
Allow Non-Secure code to access the UART[0:0] |
|
|
(23:22) I2C_ACCESS |
(23:22) I2C_ACCESS |
0x0 |
Allow Non-Secure code to access the I2C[1:0] |
|
|
(21:20) SPI_ACCESS |
(21:20) SPI_ACCESS |
0x0 |
Allow Non-Secure code to access the SPI[1:0] |
|
|
(19) GPIO_SRC_ACCESS |
(19) GPIO_SRC_ACCESS |
0x0 |
Allow Non-Secure code to access the GPIO_SRC |
|
|
(18) GPIO_ACCESS |
(18) GPIO_ACCESS |
0x0 |
Allow Non-Secure code to access the GPIO |
|
|
(17) CC312_ACCESS |
(17) CC312_ACCESS |
0x0 |
Allow Non-Secure code to access the CC312 |
|
|
(16) ASCC_ACCESS |
(16) ASCC_ACCESS |
0x0 |
Allow Non-Secure code to access the ASCC |
|
|
(15:12) TIMER_ACCESS |
(15:12) TIMER_ACCESS |
0x0 |
Allow Non-Secure code to access the Timer[3:0] |
|
|
(10) CRC_ACCESS |
(10) CRC_ACCESS |
0x0 |
Allow Non-Secure code to access the CRC |
|
|
(8) NMI_ACCESS |
(8) NMI_ACCESS |
0x0 |
Allow Non-Secure code to access the NMI |
|
|
(7) WATCHDOG_ACCESS |
(7) WATCHDOG_ACCESS |
0x0 |
Allow Non-Secure code to access the Watchdog |
|
|
(6) SYSCTRL_ACCESS |
(6) SYSCTRL_ACCESS |
0x0 |
Allow Non-Secure code to access the SYSCTRL |
|
|
(5) SENSOR_ACCESS |
(5) SENSOR_ACCESS |
0x0 |
Allow Non-Secure code to access the Sensor |
|
|
(4) ACS_ACCESS |
(4) ACS_ACCESS |
0x0 |
Allow Non-Secure code to access the ACS |
|
|
(3) LSAD_ACCESS |
(3) LSAD_ACCESS |
0x0 |
Allow Non-Secure code to access the LSAD config |
|
|
(2) TEST_CTRL_ACCESS |
(2) TEST_CTRL_ACCESS |
0x0 |
Allow Non-Secure code to access the TEST_CTRL config |
|
|
(1) CLK_ACCESS |
(1) CLK_ACCESS |
0x0 |
Allow Non-Secure code to access the CLK config |
|
|
(0) RESET_ACCESS |
(0) RESET_ACCESS |
0x0 |
Allow Non-Secure code to access the Reset |
0x40000048 |
SYSCTRL_NS_ACCESS_PERIPH_CFG1 |
(11) FLASH_IF_ACCESS |
(11) FLASH_IF_ACCESS |
0x0 |
Allow Non-Secure code to access the FLASH_IF[0:0] |
|
|
(10) RF_ACCESS |
(10) RF_ACCESS |
0x0 |
Allow Non-Secure code to access the RF |
|
|
(8) BB_ACCESS |
(8) BB_ACCESS |
0x0 |
Allow Non-Secure code to access the BB |
|
|
(3:0) DMA_ACCESS |
(3:0) DMA_ACCESS |
0x0 |
Allow Non-Secure code to access the DMA[3:0] |
0x4000004C |
SYSCTRL_NS_ACCESS_RAM_CFG0 |
(7:0) DRAM_ACCESS |
(7:0) DRAM_ACCESS |
0x0 |
Allow Non-Secure to access DRAM[7:0] |
0x40000050 |
SYSCTRL_NS_ACCESS_RAM_CFG1 |
(1:0) BB_DRAM_ACCESS |
(1:0) BB_DRAM_ACCESS |
0x0 |
Allow Non-Secure code to access BB_DRAM[1:0] |
0x4000005C |
SYSCTRL_DEU_STATUS |
(17) OVERFLOW_CLEAR |
- |
N/A |
Clear OVERFLOW flag |
|
|
(16) FIRST_DAP_W_FLAG_CLEAR |
- |
N/A |
Clear the FIRST_DAP_W_FLAG |
|
|
- |
(12) FIRST_DAP_W_FLAG |
0x0 |
First Debug access port write flag |
|
|
- |
(8) OVERFLOW |
0x0 |
High when DEU_DATA register is written before been read by any bus. Clear via CLR_OVERFLOW action bit. |
|
|
- |
(4) SBUS_W |
0x0 |
Set when SBus writes the DEU_DATA, clear when the debug access port read the DEU_DATA register |
|
|
- |
(0) DAP_W |
0x0 |
Set when the debug access port writes the DEU_DATA, clear when the SBus reads the DEU_DATA register. |
0x40000060 |
SYSCTRL_DEU_DATA |
(31:0) DEU_DATA |
(31:0) DEU_DATA |
0x0 |
Data exchange unit data |
0x40000064 |
SYSCTRL_PROD_STATUS |
(31:0) PROD_STATUS |
- |
N/A |
Production Status |
0x4000007C |
SYSCTRL_CNT_CTRL |
- |
(3) CNT_STATUS |
0x0 |
Activity counters status bit |
|
|
(2) CNT_CLEAR |
- |
N/A |
Clear activity counters |
|
|
(1) CNT_STOP |
- |
N/A |
Stop activity counters |
|
|
(0) CNT_START |
- |
N/A |
Start activity counters |
0x40000080 |
SYSCTRL_SYSCLK_CNT |
(31:0) SYSCLK_CNT |
(31:0) SYSCLK_CNT |
0x0 |
System clock counter value |
0x40000084 |
SYSCTRL_CM33_CNT |
(31:0) CM33_CNT |
(31:0) CM33_CNT |
0x0 |
CM33 activity counter value |
0x40000088 |
SYSCTRL_CBUS_CNT |
(31:0) CBUS_CNT |
(31:0) CBUS_CNT |
0x0 |
CBus-instruction activity counter value |
0x4000008C |
SYSCTRL_FLASH_READ_CNT |
(31:0) FLASH_READ_CNT |
(31:0) FLASH_READ_CNT |
0x0 |
Flash read access counter value |
0x40000094 |
SYSCTRL_CC_DCU_EN0 |
- |
(31) CC_DCU_EN_ICV_GP |
0x0 |
Always On ICV governed dcu_en0 general purpose bits |
|
|
- |
(30:28) CC_DCU_EN_ICV_EH |
0x0 |
Always On ICV governed energy harversting signature. Majority of the bis must be set to confirm the state. |
|
|
- |
(27:25) CC_DCU_EN_ICV_PRDSTATE |
0x0 |
Always On ICV governed production state identifier |
|
|
- |
(24:22) CC_DCU_EN_ICV_TCTRL_ACC |
0x0 |
Always On ICV governed test control configuration access control. Majority of the bits must be set to enable the feature |
|
|
- |
(21:19) CC_DCU_EN_ICV_TRIM_ACC |
0x0 |
Always On ICV governed MNVR and chip trim access control. Majority of the bits must be set to enable the feature |
|
|
- |
(18:16) CC_DCU_EN_ICV_NVM_ACC |
0x0 |
Always On ICV governed NVM access control. Majority of the bits must be set to enable the feature |
|
|
- |
(15:13) CC_DCU_EN_ICV_SEC_RST |
0x0 |
Always On ICV governed secure reset enable. If any of these bits are set and the part is in SE state, the cc312_top is reset |
|
|
- |
(12:10) CC_DCU_EN_ICV_SPINDEN |
0x0 |
Always On ICV governed CM33 secure non-intrusive debug enable control. Majority of the bits must be set to enable the feature |
|
|
- |
(9:7) CC_DCU_EN_ICV_SPIDEN |
0x0 |
Always On ICV governed CM33 secure intrusive debug enable control. Majority of the bits must be set to enable the feature |
|
|
- |
(6:4) CC_DCU_EN_ICV_NIDEN |
0x0 |
Always On ICV governed CM33 non-intrusive debug enable control. Majority of the bits must be set to enable the feature |
|
|
- |
(3:1) CC_DCU_EN_ICV_DBGEN |
0x0 |
Always On ICV governed CM33 debug enable control. Majority of the bits must be set to enable the feature |
|
|
- |
(0) CC_DCU_EN_ICV_SEC_RST_MASK |
0x0 |
Always On ICV governed secure reset mask used in FW |
0x40000098 |
SYSCTRL_CC_DCU_EN1 |
- |
(31:16) CC_DCU_EN_OEM_GP |
0x0 |
Always On OEM governed dcu_en1 general purpose bits |
|
|
- |
(15:13) CC_DCU_EN_OEM_SEC_RST |
0x0 |
Always On OEM governed secure reset enable. If any of these bits are set and the part is in SE state, the cc312_top is reset |
|
|
- |
(12:10) CC_DCU_EN_OEM_SPINDEN |
0x0 |
Always On OEM governed CM33 secure non-intrusive debug enable control. Majority of the bits must be set to enable the feature |
|
|
- |
(9:7) CC_DCU_EN_OEM_SPIDEN |
0x0 |
Always On OEM governed CM33 secure intrusive debug enable control. Majority of the bits must be set to enable the feature |
|
|
- |
(6:4) CC_DCU_EN_OEM_NIDEN |
0x0 |
Always On OEM governed CM33 non-intrusive debug enable control. Majority of the bits must be set to enable the feature |
|
|
- |
(3:1) CC_DCU_EN_OEM_DBGEN |
0x0 |
Always On OEM governed CM33 debug enable control. Majority of the bits must be set to enable the feature |
|
|
- |
(0) CC_DCU_EN_OEM_RESERVED |
0x0 |
Always On OEM allocated reserved bit (unused) |
0x4000009C |
SYSCTRL_CC_DCU_EN2 |
- |
(31:0) CC_DCU_EN2 |
0x0 |
Always On block DCU_EN2 state |
0x400000A0 |
SYSCTRL_CC_DCU_EN3 |
- |
(31:0) CC_DCU_EN3 |
0x0 |
Always On block DCU_EN3 state |
0x400000A4 |
SYSCTRL_CC_DCU_LOCK0 |
- |
(31) CC_DCU_LOCK_ICV_GP |
0x0 |
Always On dcu_en0 general purpose bits lock. All bits must be locked to assure that the state is locked |
|
|
- |
(30:28) CC_DCU_LOCK_ICV_EH |
0x0 |
Always On energy harvesting signature lock. All bits must be locked to assure that the state is locked |
|
|
- |
(27:25) CC_DCU_LOCK_ICV_PRDSTATE |
0x0 |
Always On production state identifier lock. All bits must be locked to assure that the state is locked |
|
|
- |
(24:22) CC_DCU_LOCK_ICV_TCTRL_ACC |
0x0 |
Always On test control configuration access control lock. All bits must be locked to assure that the state is locked |
|
|
- |
(21:19) CC_DCU_LOCK_ICV_TRIM_ACC |
0x0 |
Always On MNVR and chip trim access control lock. All bits must be locked to assure that the state is locked |
|
|
- |
(18:16) CC_DCU_LOCK_ICV_NVM_ACC |
0x0 |
Always On NVM access control lock. All bits must be locked to assure that the state is locked |
|
|
- |
(15:13) CC_DCU_LOCK_ICV_SEC_RST |
0x0 |
Always On ICV secure reset enable lock. All bits must be locked to assure that the state is locked |
|
|
- |
(12:10) CC_DCU_LOCK_ICV_SPINDEN |
0x0 |
Always On ICV CM33 secure non-intrusive debug enable control lock. All bits must be locked to assure that the state is locked |
|
|
- |
(9:7) CC_DCU_LOCK_ICV_SPIDEN |
0x0 |
Always On ICV CM33 secure intrusive debug enable control lock. All bits must be locked to assure that the state is locked |
|
|
- |
(6:4) CC_DCU_LOCK_ICV_NIDEN |
0x0 |
Always On ICV CM33 non-intrusive debug enable control lock. All bits must be locked to assure that the state is locked |
|
|
- |
(3:1) CC_DCU_LOCK_ICV_DBGEN |
0x0 |
Always On ICV CM33 debug enable control lock. All bits must be locked to assure that the state is locked |
|
|
- |
(0) CC_DCU_LOCK_ICV_SEC_RST_MASK |
0x0 |
Always On ICV secure reset mask lock |
0x400000A8 |
SYSCTRL_CC_DCU_LOCK1 |
- |
(31:16) CC_DCU_LOCK_OEM_GP |
0x0 |
Always On OEM governed dcu_en1 general purpose bits lock |
|
|
- |
(15:13) CC_DCU_LOCK_OEM_SEC_RST |
0x0 |
Always On OEM governed secure reset lock. All bits must be locked to assure that the state is locked |
|
|
- |
(12:10) CC_DCU_LOCK_OEM_SPINDEN |
0x0 |
Always On OEM governed CM33 secure non-intrusive debug enable control lock. All bits must be locked to assure that the state is locked |
|
|
- |
(9:7) CC_DCU_LOCK_OEM_SPIDEN |
0x0 |
Always On OEM governed CM33 secure intrusive debug enable control lock. All bits must be locked to assure that the state is locked |
|
|
- |
(6:4) CC_DCU_LOCK_OEM_NIDEN |
0x0 |
Always On OEM governed CM33 non-intrusive debug enable control lock. All bits must be locked to assure that the state is locked |
|
|
- |
(3:1) CC_DCU_LOCK_OEM_DBGEN |
0x0 |
Always On OEM governed CM33 debug enable control lock. All bits must be locked to assure that the state is locked |
|
|
- |
(0) CC_DCU_LOCK_OEM_RESERVED |
0x0 |
Always On OEM allocated reserved bit (unused) |
0x400000AC |
SYSCTRL_CC_DCU_LOCK2 |
- |
(31:0) CC_DCU_LOCK2 |
0x0 |
Always On block DCU_LOCK2 state |
0x400000B0 |
SYSCTRL_CC_DCU_LOCK3 |
- |
(31:0) CC_DCU_LOCK3 |
0x0 |
Always On block DCU_LOCK3 state |
0x400000B4 |
SYSCTRL_CC_STATUS |
- |
(25) CC_SEC_DEBUG_RESET |
0x0 |
Always On block secure debug reset status |
|
|
- |
(24) CC_HOST_DFA_ENABLE_LOCK |
0x0 |
Always On block host AES DFA lock status |
|
|
- |
(23) CC_HOST_FORCE_DFA_ENABLE |
0x0 |
Always On block host AES DFA status |
|
|
- |
(22) CC_RESET_UPON_DEBUG_DISABLE |
0x0 |
Always On block HUK reset mechanism configuration status |
|
|
- |
(21) CC_HOST_ICV_RMA_LOCK |
0x0 |
Always On block host icv rma bit in NVM lock status |
|
|
- |
(20) CC_HOST_KCE_LOCK |
0x0 |
Always On block host OEM code encryption key lock status |
|
|
- |
(19) CC_HOST_KCP_LOCK |
0x0 |
Always On block host OEM provisioning key lock status |
|
|
- |
(18) CC_HOST_KCEICV_LOCK |
0x0 |
Always On block host ICV code encryption key lock status |
|
|
- |
(17) CC_HOST_KPICV_LOCK |
0x0 |
Always On block host ICV provisioning key lock status |
|
|
- |
(16) CC_HOST_FATAL_ERR |
0x0 |
Always On block host fatal error flag |
|
|
- |
(15) CC_APB_ONLY_PRIV_ACCESS_LOCK |
0x0 |
Always On block APB filtering privileged access configuration lock |
|
|
- |
(14) CC_APB_ONLY_PRIV_ACCESS |
0x0 |
Always On block APB filtering privileged access configuration |
|
|
- |
(13) CC_APB_ONLY_SEC_ACCESS_LOCK |
0x0 |
Always On block APB filtering secure access configuration lock |
|
|
- |
(12) CC_APB_ONLY_SEC_ACCESS |
0x0 |
Always On block APB filtering secure access configuration |
|
|
- |
(11:4) CC_GPPC |
0x0 |
Always On block GPPC register |
|
|
- |
(3) CC_LCS_VALID |
0x0 |
Always On block life cycle state valid |
|
|
- |
(2:0) CC_LCS |
0x0 |
Always On block life cycle state |
0x400000B8 |
SYSCTRL_CC_FEATURES_CTRL |
- |
(30) CC_OEM_SEC_RST_ALL |
0x0 |
Always On block OEM governed DCU_EN bits fault status allocated for enabling SEC_RST operation |
|
|
- |
(29) CC_OEM_SPINDEN_ALL |
0x0 |
Always On block OEM governed DCU_EN bits fault status allocated for enabling SPINDEN operation |
|
|
- |
(28) CC_OEM_SPIDEN_ALL |
0x0 |
Always On block OEM governed DCU_EN bits fault status allocated for enabling SPIDEN operation |
|
|
- |
(27) CC_OEM_NIDEN_ALL |
0x0 |
Always On block OEM governed DCU_EN bits fault status allocated for enabling NIDEN operation |
|
|
- |
(26) CC_OEM_DBGEN_ALL |
0x0 |
Always On block OEM governed DCU_EN bits fault status allocated for enabling DBGEN operation |
|
|
- |
(25) CC_ENERGY_HARVESTING_ALL |
0x0 |
Always On block DCU_EN bits fault status allocated for enabling ENERGY_HARVESTING operation |
|
|
- |
(24) CC_PROD_STATUS_ALL |
0x0 |
Always On block DCU_EN bits fault status allocated for enabling PROD_STATUS operation |
|
|
- |
(23) CC_TCTRL_ACC_ALL |
0x0 |
Always On block DCU_EN bits fault status allocated for enabling TCTRL_ACC operation |
|
|
- |
(22) CC_TRIM_ACC_ALL |
0x0 |
Always On block DCU_EN bits fault status allocated for enabling TRIM_ACC operation |
|
|
- |
(21) CC_NVM_ACC_ALL |
0x0 |
Always On block DCU_EN bits fault status allocated for enabling NVM_ACC operation |
|
|
- |
(20) CC_ICV_SEC_RST_ALL |
0x0 |
Always On block ICV governed DCU_EN bits fault status allocated for enabling SEC_RST operation |
|
|
- |
(19) CC_ICV_SPINDEN_ALL |
0x0 |
Always On block ICV governed DCU_EN bits fault status allocated for enabling SPINDEN operation |
|
|
- |
(18) CC_ICV_SPIDEN_ALL |
0x0 |
Always On block ICV governed DCU_EN bits fault status allocated for enabling SPIDEN operation |
|
|
- |
(17) CC_ICV_NIDEN_ALL |
0x0 |
Always On block ICV governed DCU_EN bits fault status allocated for enabling NIDEN operation |
|
|
- |
(16) CC_ICV_DBGEN_ALL |
0x0 |
Always On block ICV governed DCU_EN bits fault status allocated for enabling DBGEN operation |
|
|
- |
(13) CC_OEM_SPINDEN |
0x0 |
Always On block OEM SPINDEN status as the result of the equality check and production state confirmation |
|
|
- |
(12) CC_OEM_SPIDEN |
0x0 |
Always On block OEM SPIDEN status as the result of the equality check and production state confirmation |
|
|
- |
(11) CC_OEM_NIDEN |
0x0 |
Always On block OEM NIDEN status as the result of the equality check and production state confirmation |
|
|
- |
(10) CC_OEM_DBGEN |
0x0 |
Always On block OEM DBGEN status as the result of the equality check and production state confirmation |
|
|
- |
(9) CC_ENERGY_HARVESTING |
0x0 |
Always On block Energy Harvesting status as the result of equality check |
|
|
- |
(8) CC_PROD_STATUS |
0x0 |
Always On block Production Status as the result of equality check |
|
|
- |
(7) CC_TCTRL_ACC |
0x0 |
Always On block TCTRL_ACC status as the result of the equality check and production state confirmation |
|
|
- |
(6) CC_TRIM_ACC |
0x0 |
Always On block TRIM_ACC status as the result of the equality check and production state confirmation |
|
|
- |
(5) CC_NVM_ACC |
0x0 |
Always On block NVM_ACC status as the result of the equality check and production state confirmation |
|
|
- |
(4) CC_SEC_RST |
0x0 |
Always On block ICV or OEM SEC_RST status as the result of any bit being set. |
|
|
- |
(3) CC_ICV_SPINDEN |
0x0 |
Always On block ICV SPINDEN status as the result of the equality check and production state confirmation |
|
|
- |
(2) CC_ICV_SPIDEN |
0x0 |
Always On block ICV SPIDEN status as the result of the equality check and production state confirmation |
|
|
- |
(1) CC_ICV_NIDEN |
0x0 |
Always On block ICV NIDEN status as the result of the equality check and production state confirmation |
|
|
- |
(0) CC_ICV_DBGEN |
0x0 |
Always On block ICV DBGEN status as the result of the equality check and production state confirmation |
0x400000D0 |
SYSCTRL_VDDPA_CFG0 |
(31:24) DISABLE_DELAY |
(31:24) DISABLE_DELAY |
0x0 |
VDDPA disable delay after ramp down (in system clock cycles) |
|
|
(23:16) RAMPUP_DELAY |
(23:16) RAMPUP_DELAY |
0x0 |
VDDPA ramp up delay after regulator enabling (in system clock cycles) |
|
|
(15:8) SW_CTRL_DELAY |
(15:8) SW_CTRL_DELAY |
0x0 |
VDDPA SW_CTRL delay after regulator enabling (in system clock cycles) |
|
|
(0) DYNAMIC_CTRL |
(0) DYNAMIC_CTRL |
0x0 |
Dynamic VDDPA control (VDDPA is enabled when RF is in TX mode, disabled otherwise) |
0x400000D4 |
SYSCTRL_VDDPA_CFG1 |
- |
(31) ACTUAL_SW_CTRL |
0x0 |
VDDPA actual SW_CTRL status |
|
|
- |
(30) ACTUAL_ENABLE |
0x0 |
VDDPA actual enable status |
|
|
- |
(29:24) ACTUAL_VTRIM |
0x0 |
VDDPA actual voltage trimming status |
|
|
(23:16) RAMPDOWN_STEP_TIME |
(23:16) RAMPDOWN_STEP_TIME |
0x0 |
VDDPA ramp down step duration (in system clock cycles) |
|
|
(15:8) RAMPUP_STEP_TIME |
(15:8) RAMPUP_STEP_TIME |
0x0 |
VDDPA ramp up step duration (in system clock cycles) |
|
|
(6:4) RAMPDOWN_STEP |
(6:4) RAMPDOWN_STEP |
0x0 |
Amount of VDDPA ramp down step(s) |
|
|
(2:0) RAMPUP_STEP |
(2:0) RAMPUP_STEP |
0x0 |
Amount of VDDPA ramp up step(s) |
0x400000D8 |
SYSCTRL_RFIF_CTRL |
(13) IQ_CLEAR |
- |
N/A |
Clear IQ data register |
|
|
(12) PHASE_ADC_CLEAR |
- |
N/A |
Clear phase ADC registers |
|
|
(11) PACKET_END_CLEAR |
- |
N/A |
Clear packet end register |
|
|
(10) CTE_MODE_CLEAR |
- |
N/A |
Clear CTE mode register |
|
|
(9) SYNC_WORD_CLEAR |
- |
N/A |
Clear sync world register |
|
|
(8) COUNTER_CLEAR |
- |
N/A |
Clear counter |
|
|
(1) IQ_STREAMING |
(1) IQ_STREAMING |
0x0 |
Enable I/Q data streaming |
|
|
(0) PHASE_ADC_STREAMING |
(0) PHASE_ADC_STREAMING |
0x0 |
Enable phase ADC data streaming |
0x400000DC |
SYSCTRL_RFIF_IQ |
- |
(15:8) Q |
0x0 |
Quadrature data |
|
|
- |
(7:0) I |
0x0 |
In-phase data |
0x400000E0 |
SYSCTRL_RFIF_PHASE_ADC |
- |
(28:24) RSSI_1 |
0x0 |
RSSI data 1 |
|
|
- |
(20:16) RSSI_0 |
0x0 |
RSSI data 0 |
|
|
- |
(15:12) AGC_1 |
0x0 |
AGC data 1 |
|
|
- |
(11:8) AGC_0 |
0x0 |
AGC data 0 |
|
|
- |
(7:4) ADC_1 |
0x0 |
Phase ADC data 1 |
|
|
- |
(3:0) ADC_0 |
0x0 |
Phase ADC data 0 |
0x400000E4 |
SYSCTRL_RFIF_PHASE_ADC_FLAGS |
- |
(31) PACKET_END_FLAG_1 |
0x0 |
Packet end flag 1 |
|
|
- |
(30) CTE_MODE_FLAG_1 |
0x0 |
CTE mode flag 1 |
|
|
- |
(29) SYNC_WORD_FLAG_1 |
0x0 |
Sync word flag 1 |
|
|
- |
(28:24) RSSI_1 |
0x0 |
RSSI data 1 |
|
|
- |
(23) PACKET_END_FLAG_0 |
0x0 |
Packet end flag 0 |
|
|
- |
(22) CTE_MODE_FLAG_0 |
0x0 |
CTE mode flag 0 |
|
|
- |
(21) SYNC_WORD_FLAG_0 |
0x0 |
Sync word flag 0 |
|
|
- |
(20:16) RSSI_0 |
0x0 |
RSSI data 0 |
|
|
- |
(15:12) AGC_1 |
0x0 |
AGC data 1 |
|
|
- |
(11:8) AGC_0 |
0x0 |
AGC data 0 |
|
|
- |
(7:4) ADC_1 |
0x0 |
Phase ADC data 1 |
|
|
- |
(3:0) ADC_0 |
0x0 |
Phase ADC data 0 |
0x400000E8 |
SYSCTRL_RFIF_PHASE_ADC_0 |
- |
(26) PACKET_END_FLAG_0 |
0x0 |
Packet end flag 0 |
|
|
- |
(25) CTE_MODE_FLAG_0 |
0x0 |
CTE mode flag 0 |
|
|
- |
(24) SYNC_WORD_FLAG_0 |
0x0 |
Sync word flag 0 |
|
|
- |
(20:16) RSSI_0 |
0x0 |
RSSI data 0 |
|
|
- |
(11:8) AGC_0 |
0x0 |
AGC data 0 |
|
|
- |
(3:0) ADC_0 |
0x0 |
Phase ADC data 0 |
0x400000EC |
SYSCTRL_RFIF_PHASE_ADC_1 |
- |
(26) PACKET_END_FLAG_1 |
0x0 |
Packet end flag 1 |
|
|
- |
(25) CTE_MODE_FLAG_1 |
0x0 |
CTE mode flag 1 |
|
|
- |
(24) SYNC_WORD_FLAG_1 |
0x0 |
Sync word flag 1 |
|
|
- |
(20:16) RSSI_1 |
0x0 |
RSSI data 1 |
|
|
- |
(11:8) AGC_1 |
0x0 |
AGC data 1 |
|
|
- |
(3:0) ADC_1 |
0x0 |
Phase ADC data 1 |
0x400000F0 |
SYSCTRL_RFIF_COUNTER |
- |
(15:0) STATE |
0xFFFF |
Current data counter state |
0x400000F4 |
SYSCTRL_RFIF_SYNC_WORD |
- |
(15:0) COUNTER_STATE |
0xFFFF |
Data counter state coinciding with the sync word detection |
0x400000F8 |
SYSCTRL_RFIF_CTE_MODE |
- |
(15:0) COUNTER_STATE |
0xFFFF |
Data counter state coinciding with the CTE mode detection |
0x400000FC |
SYSCTRL_RFIF_PACKET_END |
- |
(15:0) COUNTER_STATE |
0xFFFF |
Data counter state coinciding with the paket end detection |