CLK_DIV_CFG0
Bit Field |
Read/Write |
Field Name |
Description |
---|---|---|---|
20:16 |
RW |
UARTCLK_PRESCALE |
Prescale value for the UART peripheral clock (1 to 32 in steps of 1) |
10:8 |
RW |
BBCLK_PRESCALE |
Prescale value for the Baseband peripheral clock (1 to 8 in steps of 1) |
5:0 |
RW |
SLOWCLK_PRESCALE |
Prescale value for the SLOWCLK clock (1 to 64 in steps of 1) |
Bit Field |
Field Name |
Value Symbol |
Value Description |
Hex Value |
---|---|---|---|---|
20:16 |
UARTCLK_PRESCALE |
UARTCLK_PRESCALE_1 |
Divide by 1 |
0x0* |
|
|
UARTCLK_PRESCALE_2 |
Divide by 2 |
0x1 |
|
|
UARTCLK_PRESCALE_31 |
Divide by 31 |
0x1E |
|
|
UARTCLK_PRESCALE_32 |
Divide by 32 |
0x1F |
10:8 |
BBCLK_PRESCALE |
BBCLK_PRESCALE_1 |
Divide by 1 |
0x0* |
|
|
BBCLK_PRESCALE_2 |
Divide by 2 |
0x1 |
|
|
BBCLK_PRESCALE_3 |
Divide by 3 |
0x2 |
|
|
BBCLK_PRESCALE_4 |
Divide by 4 |
0x3 |
|
|
BBCLK_PRESCALE_5 |
Divide by 5 |
0x4 |
|
|
BBCLK_PRESCALE_6 |
Divide by 6 |
0x5 |
|
|
BBCLK_PRESCALE_7 |
Divide by 7 |
0x6 |
|
|
BBCLK_PRESCALE_8 |
Divide by 8 |
0x7 |
5:0 |
SLOWCLK_PRESCALE |
SLOWCLK_PRESCALE_1 |
Divide by 1 |
0x0 |
|
|
SLOWCLK_PRESCALE_2 |
Divide by 2 |
0x1 |
|
|
SLOWCLK_PRESCALE_3 |
Divide by 3 |
0x2* |
|
|
SLOWCLK_PRESCALE_4 |
Divide by 4 |
0x3 |
|
|
SLOWCLK_PRESCALE_6 |
Divide by 6 |
0x5 |
|
|
SLOWCLK_PRESCALE_8 |
Divide by 8 |
0x7 |
|
|
SLOWCLK_PRESCALE_10 |
Divide by 10 |
0x9 |
|
|
SLOWCLK_PRESCALE_12 |
Divide by 12 |
0xB |
|
|
SLOWCLK_PRESCALE_16 |
Divide by 16 |
0xF |
|
|
SLOWCLK_PRESCALE_24 |
Divide by 24 |
0x17 |
|
|
SLOWCLK_PRESCALE_48 |
Divide by 48 |
0x2F |
|
|
SLOWCLK_PRESCALE_63 |
Divide by 63 |
0x3E |
|
|
SLOWCLK_PRESCALE_64 |
Divide by 64 |
0x3F |