Nested Vector Interrupt Controller (NVIC)

The Arm Cortex-M33 processor is closely tied to a nested vectored interrupt controller (NVIC), which is a private peripheral provided for the processor that supports interrupt and fault handling functionality. This block is implemented with the Arm Cortex-M33 processor and is described in the ARM Cortex-M33 Technical Reference Manual.

The Arm Cortex-M33 processor as implemented for RSL15 uses pulse interrupts. These interrupts are sampled on the rising edge of SYSCLK. A pulse interrupt can be reasserted during the ISR so that the interrupt can be in the pending state and active at the same time. If another pulse arrives while the interrupt is still pending, the interrupt remains pending and the ISR runs only once.

The NVIC handles a non-maskable interrupt (NMI), predefined interrupts, several faults, and a set of general-purpose interrupts that are external to the Arm Cortex-M33 processor and are linked to its interfaces and peripherals. A list of the interrupts supported by the NVIC for the Arm Cortex-M33 processor is provided in the "Interrupts in the Arm Cortex-M33 Processor" table

IMPORTANT: For best practices in error, fault, and watchdog interrupt handling see Diagnostic Strategies from the RSL15 Developer's Guide.

Table: Interrupts in the Arm Cortex-M33 Processor

Interrupt Enumeration Define

Enumeration Value

Vector Number

Description

Reset_IRQn

-15

1

Reset vector

NonMaskableInt_IRQn

-14

2

Non-maskable interrupt (NMI)

HardFault_IRQn

-13

3

Hard fault interrupt

MemoryManagement_IRQn

-12

4

Memory management interrupt

BusFault_IRQn

-11

5

Bus fault interrupt

UsageFault_IRQn

-10

6

Usage fault interrupt

SecureFault_IRQn

-9

7

Secure fault interrupt

SVCall_IRQn

-5

11

SVCall interrupt

DebugMonitor_IRQn

-4

12

Debug monitor interrupt

PendSV_IRQn

-2

14

PendSV interrupt

SysTick_IRQn

-1

15

System Tick interrupt

WAKEUP_IRQn

0

16

Wake-up interrupt

RTC_ALARM_IRQn

1

17

RTC alarm interrupt

RTC_CLOCK_IRQn

2

18

RTC clock interrupt

LSAD_MONITOR_IRQn

3

19

LSAD and voltage monitoring interrupt

TIMER0_IRQn

4

20

Timer 0 interrupt

TIMER1_IRQn

5

21

Timer 1 interrupt

TIMER2_IRQn

6

22

Timer 2 interrupt

TIMER3_IRQn

7

23

Timer 3 interrupt

FIFO_IRQn

8

24

FIFO interrupt

GPIO0_IRQn

9

25

GPIO 0 interrupt

GPIO1_IRQn

10

26

GPIO 1 interrupt

GPIO2_IRQn

11

27

GPIO 2 interrupt

GPIO3_IRQn

12

28

GPIO 3 interrupt

WATCHDOG_IRQn

13

29

Watchdog interrupt

SPI0_RX_IRQn

14

30

SPI0 receive interrupt

SPI0_TX_IRQn

15

31

SPI0 transmit interrupt

SPI0_COM_IRQn

16

32

SPI0 common interrupt

SPI1_RX_IRQn

17

33

SPI1 receive interrupt

SPI1_TX_IRQn

18

34

SPI1 transmit interrupt

SPI1_COM_IRQn

19

35

SPI1 common interrupt

I2C0_IRQn

20

36

I2C 0 interrupt

I2C1_IRQn

21

37

I2C 1 interrupt

UART0_RX_IRQn

22

38

UART receive interrupt

UART0_TX_IRQn

23

39

UART transmit interrupt

UART0_ERROR_IRQn

24

40

UART common interrupt

PCM0_RX_TX_IRQn

25

41

PCM receive/transmit interrupt

PCM0_ERROR_IRQn

26

42

PCM error interrupt

LIN0_IRQn

27

43

LIN interrupt

FPU_IRQn

28

44

Floating point unit exception interrupt

CC312_IRQn

29

45

CryptoCell (CC312) interrupt

ASCC_PHASE_IRQn

30

46

Asynchronous clock counter phase interrupt

ASCC_PERIOD_IRQn

31

47

Asynchronous clock counter period interrupt

BLE_SW_IRQn

32

48

Bluetooth Low Energy SW triggered interrupt

BLE_FINETGT_IRQn

33

49

Bluetooth Low Energy fine timer target interrupt

BLE_TIMESTAMP_TGT1_IRQn

34

50

Bluetooth Low Energy time stamp target 1 interrupt (generated at a defined instant)

BLE_TIMESTAMP_TGT2_IRQn

35

51

Bluetooth Low Energy time stamp target 2 interrupt (generated at a defined instant)

BLE_CRYPT_IRQn

36

52

Bluetooth Low Energy AES ciphering complete interrupt

BLE_SLP_IRQn

37

53

Bluetooth Low Energy sleep mode interrupt (generated at the end of a sleep period)

BLE_HSLOT_IRQn

38

54

Bluetooth Low Energy half slot interrupt (generated every 312.5 μs)

BLE_FIFO_IRQn

39

55

Bluetooth Low Energy FIFO activity interrupt

BLE_ERROR_IRQn

40

56

Bluetooth Low Energy error interrupt

BLE_COEX_IN_PROCESS_IRQn

41

57

RF coexistence - Bluetooth Low Energy technology in process interrupt

BLE_COEX_RX_TX_IRQn

42

58

RF coexistence - Bluetooth Low Energy technology start/stop Rx or Tx interrupt

TOF_IRQn

43

59

Time of flight counter interrupt

RF_TX_IRQn

44

60

RF end of packet transmission transmit interrupt

RF_RXSTOP_IRQn

45

61

RF receive stop interrupt

RF_IRQ_RECEIVED_IRQn

46

62

RF received packet interrupt

RF_SYNC_IRQn

47

63

RF received sync word interrupt

RF_TXFIFO_IRQn

48

64

RF Tx FIFO near underflow detect interrupt

RF_RXFIFO_IRQn

49

64

RF Rx FIFO near overflow detect interrupt

FLASH0_COPY_IRQn

50

66

Flash copy interrupt

FLASH0_ECC_IRQn

51

67

Flash ECC event interrupt

ACCESS_ERROR_IRQn

52

68

Memory and peripheral error interrupt

DMA0_IRQn

53

69

DMA 0 interrupt

DMA1_IRQn

54

70

DMA 1 interrupt

DMA2_IRQn

55

71

DMA 2 interrupt

DMA3_IRQn

56

72

DMA 3 interrupt

Interrupt Priority Registers

Use the Interrupt Priority Registers (NVIC_IP*) to assign a priority to each of the available interrupts. Each byte in an Interrupt Priority can be used to set the priority for one of the external interrupts (vectors 16 to 72) listed in Interrupts in the Arm Cortex-M33 Processor (table).

NOTE: Configuration of the interrupt priorities for standard Arm Cortex-M33 processor exceptions (vectors 4 to 15) are set using the System Handler Priority registers. For more information, see the ARMv8M Architecture Reference Manual.

The NVIC for the Arm Cortex-M33 processor in the RSL15 system has been implemented with three interrupt priority bits per interrupt. These three priority bits are MSB aligned to an eight-bit priority bit field as required by Arm. Generally, the lower the priority value, the higher the priority that interrupt is given.

The interrupt priority settings are divided into interrupt priority groups, configured using the SCB_AIRCR register, with preemption in lower numbered groups with interrupts within a group sorted by interrupt priority settings and finally if required sorted by vector number. Interrupts can be further prioritized to deprioritize all non-secure interrupts when one or more secure interrupts are pending. When choosing which interrupt to activate, the priority settings are applied as follows:

  • When multiple interrupts are pending, but no interrupts are active, the interrupt with the lowest priority setting is activated. If more than one pending interrupt shares the lowest priority setting, the interrupt with the lower vector number is activated.
  • If an interrupt is currently active, it can be pre-empted by any interrupt that is pended in a lower numbered group. If multiple interrupts that could pre-empt the active interrupt are pending, the interrupt with the lowest priority setting is activated. As before, if more than one pending interrupt shares the lowest priority setting, the interrupt with the lower vector number is activated.

IMPORTANT: The reset, NMI and fault vectors have priority levels of -3, -2, and -1 respectively. As such, these events can always pre-empt interrupts with lower priorities.

For this peripheral’s registers, see NVIC Registers.