Continuous Wave (CW) Configuration

In the course of your output power and frequency testing, you might need to configure the RF front-end to output a CW signal. For instance, if your testing equipment uses a frequency divider/counter to measure output frequency, it requires RSL15 to output an unmodulated signal.

The following steps describe how to use register settings to configure a CW signal output, for TX or RX, at a rate of either 1 Mbps or 2 Mbps:

  1. Load the hci hex file into flash memory, and then reset the RSL15 Evaluation and Development Board. The RSL15 RF Tools offer two menus where RSL15 can be put in CW mode, RX or TX, at the desired frequency. For TX, output power can be also set from RF Tools. If CW Mode needs to be handled in FW, the following settings need to be applied:
    1. Set the RF_REG00_MODE2_TESTMODE bit from the RF_REG00 register to 0:
    2. Select register bank 0 :
    3. RF0_REG08->BANK_BYTE = 0x4;
  2. Set the RF_CENTER_FREQ register to the frequency you desire, and disable Bluetooth Low Energy channel selection. It is possible specify the desired Bluetooth Low Energy channel number whiteout setting the center frequency and disabling channel selection. Find the required frequency using the equation in the following code:

center_freq = (((float)freq* (0x1 << 21)) / 144000000.0); /* frequency is in Hz */

RF->CENTER_FREQ = (CENTER_FREQ_ADAPT_CFREQ_ENABLE | center_freq);

RF->CODING &= (~CHANNELS_2_EN_CHANNEL_SEL_ENABLE);

RF->CODING &= (~CHANNELS_2_EN_CHN_BLE_ENABLE);

  1. RF0_REG08->BANK_BYTE is set to 0, for 1 Mbps, by default. For 2 Mbps, set RF0_REG08->BANK_BYTE to 1.6.
  2. To configure for RX mode, use RF0_FSM_CTRL->FSM_MODE_BYTE = (FSM_MODE_MODE_CAL_PLL_TXRX | FSM_MODE_RX_NTX);.
  3. To configure for TX mode, use RF0_FSM_CTRL->FSM_MODE_BYTE = (FSM_MODE_MODE_CAL_PLL_TXRX | FSM_MODE_TX_NRX);.
  4. To configure for idle mode (disable RF), set RF_REG30->FSM_MODE_BYTE to 8.

When working in CW configuration, use your own preferred settings for VDDRF, VDDPA enabling, VCC, VDDPA, DCCLK, the charge pump clock, and buck enabling.