ACS
Address |
Register Name |
Register Write |
Register Read |
Default |
Description |
---|---|---|---|---|---|
0x40001B00 |
ACS_BG_CTRL |
- |
(31) READY |
0x0 |
Bandgap ready |
|
|
(28:24) SLOPE_ITRIM |
(28:24) SLOPE_ITRIM |
0x17 |
Current temperature coefficient trimming |
|
|
(21:16) ITRIM |
(21:16) ITRIM |
0x24 |
Reference current trimming |
|
|
(13) SEL_VTRIM_SRC |
(13) SEL_VTRIM_SRC |
0x1 |
Select trim source for SLOPE_VTRIM and VTRIM |
|
|
(12:8) SLOPE_VTRIM |
(12:8) SLOPE_VTRIM |
0x18 |
Voltage temperature coefficient trimming |
|
|
(5:0) VTRIM |
(5:0) VTRIM |
0x15 |
Reference voltage trimming (5 mV steps) |
0x40001B04 |
ACS_VCC_CTRL |
- |
(24) READY |
0x0 |
Supply ready (only makes sense in test mode) |
|
|
(21:16) VTRIM_LIMIT |
(21:16) VTRIM_LIMIT |
0x1F |
Max VTRIM value that can be used. If VTRIM value is greater it will be limited to this value |
|
|
(15:12) ICH_TRIM |
(15:12) ICH_TRIM |
0x4 |
Inductor charge current trimming |
|
|
(11) CCM_ENABLE |
(11) CCM_ENABLE |
0x0 |
Enable CCM mode |
|
|
(10) PULSE_CTRL |
(10) PULSE_CTRL |
0x0 |
Pulse mode control |
|
|
(9) CHARGE_CTRL |
(9) CHARGE_CTRL |
0x1 |
Charge mode control |
|
|
(8) BUCK_ENABLE |
(8) BUCK_ENABLE |
0x0 |
Enable buck converter mode |
|
|
(5:0) VTRIM |
(5:0) VTRIM |
0x14 |
Output voltage trimming configuration in 10 mV steps |
0x40001B08 |
ACS_VDDCP_CTRL |
- |
(24) READY |
0x0 |
Supply ready |
|
|
(13) COMP_ENABLE |
(13) COMP_ENABLE |
0x1 |
Force cp comparator enable |
|
|
(11:8) CPCLK_FREQ |
(11:8) CPCLK_FREQ |
0x2 |
Charge Pump clock frequency during power down modes |
|
|
(1:0) PTRIM |
(1:0) PTRIM |
0x3 |
Output power trimming |
0x40001B0C |
ACS_VDDC_CTRL |
- |
(24) READY |
0x0 |
Supply ready |
|
|
(21:16) STANDBY_VTRIM |
(21:16) STANDBY_VTRIM |
0x2D |
VDDC standby voltage trimming (10 mV steps) |
|
|
(12) ENABLE_LOW_BIAS |
(12) ENABLE_LOW_BIAS |
0x0 |
Low power mode control |
|
|
(8) SLEEP_CLAMP |
(8) SLEEP_CLAMP |
0x0 |
Sleep mode clamp control |
|
|
(5:0) VTRIM |
(5:0) VTRIM |
0x23 |
Output voltage trimming configuration in 10 mV steps |
0x40001B10 |
ACS_VDDM_CTRL |
- |
(24) READY |
0x0 |
Supply ready |
|
|
(21:16) STANDBY_VTRIM |
(21:16) STANDBY_VTRIM |
0x2D |
VDDM standby voltage trimming (10 mV steps) |
|
|
(12) ENABLE_LOW_BIAS |
(12) ENABLE_LOW_BIAS |
0x0 |
Low power mode control |
|
|
(8) SLEEP_CLAMP |
(8) SLEEP_CLAMP |
0x0 |
Sleep mode clamp control |
|
|
(5:0) VTRIM |
(5:0) VTRIM |
0x28 |
Output voltage trimming configuration in 10 mV steps |
0x40001B14 |
ACS_VDDPA_CTRL |
(19:16) INITIAL_VTRIM |
(19:16) INITIAL_VTRIM |
0x0 |
Initial output voltage trimming configuration in 10 mV steps |
|
|
(12) VDDPA_SW_CTRL |
(12) VDDPA_SW_CTRL |
0x0 |
Power amplifier supply control |
|
|
(9) ENABLE_ISENSE |
(9) ENABLE_ISENSE |
0x0 |
Enable current sensing circuit |
|
|
(8) ENABLE |
(8) ENABLE |
0x0 |
Enable control |
|
|
(5:0) VTRIM |
(5:0) VTRIM |
0x37 |
Output voltage trimming configuration in 10 mV steps |
0x40001B18 |
ACS_VDDRF_CTRL |
- |
(24) READY |
0x0 |
Supply ready |
|
|
(12) CLAMP |
(12) CLAMP |
0x0 |
Disable mode clamp control |
|
|
(8) ENABLE |
(8) ENABLE |
0x0 |
Enable control |
|
|
(5:0) VTRIM |
(5:0) VTRIM |
0x23 |
Output voltage trimming configuration in 10 mV steps |
0x40001B1C |
ACS_VDDFLASH_CTRL |
- |
(24) READY |
0x0 |
Supply ready |
|
|
(11) MASK_READY |
(11) MASK_READY |
0x0 |
Apply a mask to reset logic to ignore VDDFLASH ready signal |
|
|
(10) SOFT_START |
(10) SOFT_START |
0x1 |
Current limiter threshold setting |
|
|
(9) ENABLE_LIMITER |
(9) ENABLE_LIMITER |
0x1 |
Enable current limiter circuit |
|
|
(8) ENABLE |
(8) ENABLE |
0x1 |
Enable control |
|
|
(5:0) VTRIM |
(5:0) VTRIM |
0x28 |
Output voltage trimming configuration in 25 mV steps |
0x40001B20 |
ACS_VDDRET_CTRL |
(18:17) VDDMRET_VTRIM |
(18:17) VDDMRET_VTRIM |
0x3 |
VDDMRET retention regulator voltage trimming |
|
|
(16) VDDMRET_ENABLE |
(16) VDDMRET_ENABLE |
0x0 |
Enable/Disable the VDDMRET retention regulator |
|
|
(10:9) VDDACS_VTRIM |
(10:9) VDDACS_VTRIM |
0x3 |
VDDACS regulator voltage trimming |
|
|
(8) VDDTRET_ENABLE |
(8) VDDTRET_ENABLE |
0x0 |
Enables the VDDT retention power (activate switch from VDDACS) |
|
|
(2:1) VDDCRET_VTRIM |
(2:1) VDDCRET_VTRIM |
0x3 |
VDDCRET Retention regulator voltage trimming |
|
|
(0) VDDCRET_ENABLE |
(0) VDDCRET_ENABLE |
0x0 |
Enables the VDDCRET Retention regulator |
0x40001B24 |
ACS_RCOSC_CTRL |
(26:25) RC_FSEL |
(26:25) RC_FSEL |
0x0 |
Select RC oscillator frequency |
|
|
(24) RC_OSC_EN |
(24) RC_OSC_EN |
0x0 |
Enable/Disable the RC Oscillator |
|
|
(23) RC_FTRIM_FLAG |
(23) RC_FTRIM_FLAG |
0x0 |
RC Oscillator Trimming flag |
|
|
(22) RC_FTRIM_ADJ |
(22) RC_FTRIM_ADJ |
0x0 |
Adjust RC oscillator frequency range |
|
|
(21:16) RC_FTRIM |
(21:16) RC_FTRIM |
0x20 |
RC oscillator frequency trimming |
|
|
(15:14) RC32_VDDLOC_ITRIM |
(15:14) RC32_VDDLOC_ITRIM |
0x0 |
VDDLOC current trimming |
|
|
(13:12) RC32_VDDLOC_VTRIM |
(13:12) RC32_VDDLOC_VTRIM |
0x0 |
VDDLOC voltage trimming |
|
|
(9) RC32_VDDLOC_OD_EN |
(9) RC32_VDDLOC_OD_EN |
0x0 |
Enable the overdrive of vddloc with VBAT |
|
|
(8) RC32_OSC_EN |
(8) RC32_OSC_EN |
0x0 |
Enable/Disable the 32 kHz RC Oscillator |
|
|
(7) RC32_TEMP_COMP_EN |
(7) RC32_TEMP_COMP_EN |
0x0 |
Enable/Disable the 32 kHz RC Oscillator |
|
|
(6) RC32_FTRIM_ADJ |
(6) RC32_FTRIM_ADJ |
0x0 |
Adjust 32 kHz RC oscillator frequency range |
|
|
(5:0) RC32_FTRIM |
(5:0) RC32_FTRIM |
0x20 |
32 kHz RC oscillator frequency trimming |
0x40001B28 |
ACS_XTAL32K_CTRL |
(26) XTAL_N_OK_RESET |
- |
N/A |
Reset Xtal not ok sticky flag |
|
|
- |
(25) XTAL_N_OK |
0x0 |
Xtal not ready sticky flag |
|
|
- |
(24) READY |
0x0 |
Xtal ready status |
|
|
(18) XIN_CAP_BYPASS_EN |
(18) XIN_CAP_BYPASS_EN |
0x0 |
Switch to bypass the added XIN serial cap to reduce the leakage |
|
|
(17) EN_AMPL_CTRL |
(17) EN_AMPL_CTRL |
0x1 |
Xtal enable amplitude control (regulation) |
|
|
(16) FORCE_READY |
(16) FORCE_READY |
0x0 |
Xtal bypass the ready detector |
|
|
(13:8) CLOAD_TRIM |
(13:8) CLOAD_TRIM |
0x16 |
Xtal load capacitance configuration |
|
|
(7:4) ITRIM |
(7:4) ITRIM |
0x7 |
Xtal current trimming |
|
|
(1) IBOOST |
(1) IBOOST |
0x0 |
Xtal current boosting (4x) |
|
|
(0) ENABLE |
(0) ENABLE |
0x0 |
Enable the Xtal 32 kHz oscillator |
0x40001B2C |
ACS_ACOMP_CFG |
(22:20) ACOMP_PRE_SEL_ODD |
(22:20) ACOMP_PRE_SEL_ODD |
0x0 |
Pre selection of odd GPIOs |
|
|
(18:16) ACOMP_PRE_SEL_EVEN |
(18:16) ACOMP_PRE_SEL_EVEN |
0x0 |
Pre selection of even GPIOs |
|
|
(14:12) ACOMP_IN_P |
(14:12) ACOMP_IN_P |
0x2 |
Defines the positive input signal |
|
|
(10:8) ACOMP_IN_N |
(10:8) ACOMP_IN_N |
0x2 |
Defines the negative input signal |
|
|
(6:4) ACOMP_HYST |
(6:4) ACOMP_HYST |
0x0 |
Hysteresis level |
|
|
(2:1) MODE |
(2:1) MODE |
0x1 |
Power mode selection |
|
|
(0) ENABLE |
(0) ENABLE |
0x0 |
Enable signal |
0x40001B30 |
ACS_ACOMP_OUT |
- |
(0) ACOMP_OUT |
0x0 |
Comparison result |
0x40001B34 |
ACS_SDAC_CFG |
(2) SDAC_TO_GPIO7 |
(2) SDAC_TO_GPIO7 |
0x0 |
GPIO7 drive by SDAC |
|
|
(1) SDAC_GAIN |
(1) SDAC_GAIN |
0x0 |
Sets the SDAC buffer gain |
|
|
(0) SDAC_EN |
(0) SDAC_EN |
0x0 |
Enable signal for SDAC buffer |
0x40001B38 |
ACS_WEDAC_CTRL |
(5:0) WEDAC |
(5:0) WEDAC |
0x26 |
WEDAC setting |
0x40001B3C |
ACS_RTC_CFG |
(6:4) RTC_CLOCK_SRC |
(6:4) RTC_CLOCK_SRC |
0x0 |
Select the RTC Clock event source |
|
|
(2:0) CLK_SRC_SEL |
(2:0) CLK_SRC_SEL |
0x0 |
Select the RTC, standby, bb timer, and sensor block clock source |
0x40001B40 |
ACS_RTC_CTRL |
- |
(18) ENABLE_CLOCK_EVENT_STATUS |
0x0 |
Status of the RTC clock event enable |
|
|
- |
(17) ENABLE_ALARM_EVENT_STATUS |
0x0 |
Status of the RTC alarm event enable |
|
|
- |
(16) ENABLE_STATUS |
0x0 |
Status of the RTC enable |
|
|
(7) FORCE_CLOCK |
- |
N/A |
Force a clock on RTC timer (Test Purpose) |
|
|
(6) DISABLE_CLOCK_EVENT |
- |
N/A |
Disable clock event and its interrupt |
|
|
(5) ENABLE_CLOCK_EVENT |
- |
N/A |
Enable clock event and its interrupt |
|
|
(4) DISABLE_ALARM_EVENT |
- |
N/A |
Disable alarm event and its interrupt |
|
|
(3) ENABLE_ALARM_EVENT |
- |
N/A |
Enable alarm event and its interrupt |
|
|
(2) RESET |
- |
N/A |
Reset the RTC timer |
|
|
(1) DISABLE |
- |
N/A |
Disable counter and RTC interrupt every 1s |
|
|
(0) ENABLE |
- |
N/A |
Enable counter and RTC interrupt every 1s |
0x40001B44 |
ACS_RTC_COUNT_THRES |
(31:0) THRESHOLD |
(31:0) THRESHOLD |
0xFFFFFFFF |
Compare value for the RTC counter |
0x40001B48 |
ACS_RTC_COUNT |
- |
(31:0) VALUE |
0x0 |
RTC timer current value |
0x40001B4C |
ACS_RTC_SECONDS |
- |
(16:0) VALUE |
0x0 |
RTC timer current value in seconds |
0x40001B50 |
ACS_RTC_COUNT_LOAD |
(31:0) VALUE |
- |
N/A |
Load the RTC timer current value |
0x40001B54 |
ACS_BB_TIMER_CTRL |
(0) BB_TIMER_NRESET |
(0) BB_TIMER_NRESET |
0x0 |
nReset signal for the baseband timer |
0x40001B58 |
ACS_CLK_DET_CTRL |
- |
(8) CLOCK_PRESENT |
0x1 |
Clock present flag |
|
|
(1) RESET_IGNORE |
(1) RESET_IGNORE |
0x0 |
Clock detector reset condition ignore |
|
|
(0) ENABLE |
(0) ENABLE |
0x1 |
Clock detector enable |
0x40001B5C |
ACS_PWR_MODES_CTRL |
(31:0) POWER_MODE |
- |
N/A |
32-bit key to enter STANDBY, SLEEP, or DEEP_SLEEP mode. This register must be written using a 32-bit access. |
0x40001B60 |
ACS_SLEEP_MODE_CFG |
(2) BG_ENABLE |
(2) BG_ENABLE |
0x0 |
Keep Band-gap enabled during sleep |
|
|
(1) VCC_ENABLE |
(1) VCC_ENABLE |
0x0 |
Keep VCC low power enabled during sleep |
|
|
(0) VDDCP_ENABLE |
(0) VDDCP_ENABLE |
0x0 |
Keep VDDCP charge pump enabled during sleep |
0x40001B64 |
ACS_WAKEUP_CTRL |
- |
(27) RTC_OVERFLOW_WAKEUP |
0x0 |
Indicate if RTC overflow has triggered a wake-up event |
|
|
- |
(26) RTC_CLOCK_WAKEUP |
0x0 |
Indicate if RTC clock has triggered a wake-up event |
|
|
- |
(25) RTC_ALARM_WAKEUP |
0x0 |
Indicate if RTC alarm has triggered a wake-up event |
|
|
- |
(24) THRESHOLD_WAKEUP |
0x0 |
Indicate if the sensor interface threshold has triggered a wake-up event |
|
|
- |
(23) FIFO_FULL_WAKEUP |
0x0 |
Indicate if the sensor interface FIFO has triggered a wake-up event |
|
|
- |
(22) ACOMP_WAKEUP |
0x0 |
Indicate if ACOMP has triggered a wake-up event |
|
|
- |
(21) DCDC_OVERLOAD_WAKEUP |
0x0 |
Indicate if DCDC overload has triggered a wake-up event |
|
|
- |
(20) BB_TIMER_WAKEUP |
0x0 |
Indicate if baseband timer has triggered a wake-up event |
|
|
- |
(19) GPIO3_WAKEUP |
0x0 |
Indicate if GPIO3 has triggered a wake-up event |
|
|
- |
(18) GPIO2_WAKEUP |
0x0 |
Indicate if GPIO2 has triggered a wake-up event |
|
|
- |
(17) GPIO1_WAKEUP |
0x0 |
Indicate if GPIO1 has triggered a wake-up event |
|
|
- |
(16) GPIO0_WAKEUP |
0x0 |
Indicate if GPIO0 has triggered a wake-up event |
|
|
(11) THRESHOLD_WAKEUP_CLEAR |
- |
N/A |
Reset the sticky WAKEUP_THRESHOLD_EVENT flag |
|
|
(10) FIFO_FULL_WAKEUP_CLEAR |
- |
N/A |
Reset the sticky WAKEUP_FIFO_FULL_EVENT flag |
|
|
(9) ACOMP_WAKEUP_CLEAR |
- |
N/A |
Reset the sticky WAKEUP_ACOMP_EVENT flag |
|
|
(8) DCDC_OVERLOAD_WAKEUP_CLEAR |
- |
N/A |
Reset the sticky WAKEUP_DCDC_OVERLOAD flag |
|
|
(7) RTC_OVERFLOW_WAKEUP_CLEAR |
- |
N/A |
Reset the sticky WAKEUP_RTC_OVERFLOW_EVENT flag |
|
|
(6) RTC_CLOCK_WAKEUP_CLEAR |
- |
N/A |
Reset the sticky WAKEUP_RTC_CLOCK_EVENT flag |
|
|
(5) RTC_ALARM_WAKEUP_CLEAR |
- |
N/A |
Reset the sticky WAKEUP_RTC_ALARM_EVENT flag |
|
|
(4) BB_TIMER_WAKEUP_CLEAR |
- |
N/A |
Reset the sticky WAKEUP_BB_TIMER_EVENT flag |
|
|
(3) GPIO3_WAKEUP_CLEAR |
- |
N/A |
Reset the sticky WAKEUP_GPIO3_EVENT flag |
|
|
(2) GPIO2_WAKEUP_CLEAR |
- |
N/A |
Reset the sticky WAKEUP_GPIO2_EVENT flag |
|
|
(1) GPIO1_WAKEUP_CLEAR |
- |
N/A |
Reset the sticky WAKEUP_GPIO1_EVENT flag |
|
|
(0) GPIO0_WAKEUP_CLEAR |
- |
N/A |
Reset the sticky WAKEUP_GPIO0_EVENT flag |
0x40001B68 |
ACS_WAKEUP_CFG |
(18:16) DELAY |
(18:16) DELAY |
0x4 |
Delay from VDDD ready to digital clock enable (power of 2) |
|
|
(11) DCDC_OVERLOAD_EN |
(11) DCDC_OVERLOAD_EN |
0x0 |
Enable / Disable the Wake-up functionality on the DCDC overload flag |
|
|
(9) FIFO_FULL_EN |
(9) FIFO_FULL_EN |
0x0 |
Enable the wake-up on full FIFO |
|
|
(8) RTC_OVERFLOW_EN |
(8) RTC_OVERFLOW_EN |
0x0 |
Enable / Disable the Wake-up functionality on RTC overflow flag |
|
|
(7) GPIO3_POL |
(7) GPIO3_POL |
0x0 |
Wake-up polarity on the GPIO3 pad |
|
|
(6) GPIO2_POL |
(6) GPIO2_POL |
0x0 |
Wake-up polarity on the GPIO2 pad |
|
|
(5) GPIO1_POL |
(5) GPIO1_POL |
0x0 |
Wake-up polarity on the GPIO1 pad |
|
|
(4) GPIO0_POL |
(4) GPIO0_POL |
0x0 |
Wake-up polarity on the GPIO0 pad |
|
|
(3) GPIO3_EN |
(3) GPIO3_EN |
0x0 |
Enable the wake-up functionality on the GPIO3 pad |
|
|
(2) GPIO2_EN |
(2) GPIO2_EN |
0x0 |
Enable the wake-up functionality on the GPIO2 pad |
|
|
(1) GPIO1_EN |
(1) GPIO1_EN |
0x0 |
Enable the wake-up functionality on the GPIO1 pad |
|
|
(0) GPIO0_EN |
(0) GPIO0_EN |
0x0 |
Enable the wake-up functionality on the GPIO0 pad |
0x40001B6C |
ACS_WAKEUP_STATE |
- |
(19:16) WAKEUP_SRC |
0x0 |
Status register indicates the last wake-up source |
|
|
- |
(7:0) RTC_VALUE |
0x0 |
RTC counter value captured at wakeup event (only 8 LSBs, corresponds to 7.8 ms) |
0x40001B70 |
ACS_BOOT_CFG |
(8) PADS_RETENTION_EN |
(8) PADS_RETENTION_EN |
0x0 |
Enable / Disable the retention mode of the pads |
|
|
(6) BOOT_ROT_BYPASS |
(6) BOOT_ROT_BYPASS |
0x0 |
Boot bypass execution of root of trust |
|
|
(5) BOOT_PWR_CAL_BYPASS |
(5) BOOT_PWR_CAL_BYPASS |
0x0 |
Boot bypass execution of system calibration |
|
|
- |
(4:3) RC_CLOCK_FSEL |
0x0 |
RC oscillator clock multiplier read only flag (mirror of CLOCK_MULT of ACS_RCOSC_CTRL register) |
|
|
- |
(2) RC_FTRIM_FLAG |
0x0 |
RC oscillator trimming read only flag (mirror of FTRIM_FLAG of ACS_RCOSC_CTRL register |
|
|
(1:0) BOOT_SELECT |
(1:0) BOOT_SELECT |
0x0 |
Boot selection to indicate boot source |
0x40001B74 |
ACS_BOOT_GP_DATA |
(31:0) GP_DATA |
(31:0) GP_DATA |
0x0 |
32-bit General-Purpose RW Data |
0x40001B78 |
ACS_RESET_STATUS |
- |
(25) CCAO_REBOOT_RESET_FLAG |
0x1 |
Sticky flag that detects that a CryptoCell Alway ON reboot reset occurred |
|
|
- |
(24) WRONG_STATE_RESET_FLAG |
0x1 |
Sticky flag that detects that a wrong state reset occurred |
|
|
- |
(23) TIMEOUT_RESET_FLAG |
0x1 |
Sticky flag that detects that a timeout in the power up sequence occurred |
|
|
- |
(22) CLK_DET_RESET_FLAG |
0x1 |
Sticky flag that detects that a clock detector reset occurred |
|
|
- |
(21) VDDFLASH_RESET_FLAG |
0x1 |
Sticky flag that detects that a VDDFLASH reset occurred (triggered by VDDFLASH_ready = 0) |
|
|
- |
(20) VDDM_RESET_FLAG |
0x1 |
Sticky flag that detects that a VDDM reset occurred (triggered by VDDM_ready = 0) |
|
|
- |
(19) VDDC_RESET_FLAG |
0x1 |
Sticky flag that detects that a VDDC reset occurred (triggered by VDDC_ready = 0) |
|
|
- |
(18) BG_VREF_RESET_FLAG |
0x1 |
Sticky flag that detects that a Bandagap reference voltage reset occurred |
|
|
- |
(17) PAD_RESET_FLAG |
0x1 |
Sticky flag that detects that a reset occurred due to pad NRESET |
|
|
- |
(16) POR_RESET_FLAG |
0x1 |
Sticky flag that detects that a POR reset occurred |
|
|
(9) CCAO_REBOOT_RESET_FLAG_CLEAR |
- |
N/A |
Reset the sticky CCAO_REBOOT_RESET flag. |
|
|
(8) WRONG_STATE_RESET_FLAG_CLEAR |
- |
N/A |
Reset the sticky WRONG_STATE_RESET flag. |
|
|
(7) TIMEOUT_RESET_FLAG_CLEAR |
- |
N/A |
Reset the sticky TIMEOUT_RESET flag. |
|
|
(6) CLK_DET_RESET_FLAG_CLEAR |
- |
N/A |
Reset the sticky CLK_DET_RESET flag. |
|
|
(5) VDDFLASH_RESET_FLAG_CLEAR |
- |
N/A |
Reset the sticky VDDFLASH_RESET flag. |
|
|
(4) VDDM_RESET_FLAG_CLEAR |
- |
N/A |
Reset the sticky VDDM_RESET flag. |
|
|
(3) VDDC_RESET_FLAG_CLEAR |
- |
N/A |
Reset the sticky VDDC_RESET flag. |
|
|
(2) BG_VREF_RESET_FLAG_CLEAR |
- |
N/A |
Reset the sticky BG_VREF_RESET flag. |
|
|
(1) PAD_RESET_FLAG_CLEAR |
- |
N/A |
Reset the sticky PAD_RESET flag. |
|
|
(0) POR_RESET_FLAG_CLEAR |
- |
N/A |
Reset the sticky POR_RESET flag. |
0x40001B7C |
ACS_AOUT_CTRL |
(21) RTC_CLOCK_GPIO0_STOP_EDGE |
(21) RTC_CLOCK_GPIO0_STOP_EDGE |
0x0 |
Stop edge for RTC clock output on AOUT |
|
|
(20:19) RTC_CLOCK_GPIO0_STOP_SRC |
(20:19) RTC_CLOCK_GPIO0_STOP_SRC |
0x0 |
Stop source for RTC clock output on AOUT |
|
|
(18:16) RTC_CLOCK_GPIO0_START |
(18:16) RTC_CLOCK_GPIO0_START |
0x0 |
Start event for RTC clock output on AOUT (RTC prescaler and counter need to be enabled) |
|
|
(13) AOUT_IOUT_SEL_TO_GPIO |
(13) AOUT_IOUT_SEL_TO_GPIO |
0x1 |
Selection between AOUT voltage or PTAT current source to GPIO |
|
|
(12:8) AOUT_TO_GPIO |
(12:8) AOUT_TO_GPIO |
0x10 |
Select to which GPIO the AOUT voltage or PTAT current provided |
|
|
(5:0) TEST_AOUT |
(5:0) TEST_AOUT |
0x0 |
AOUT test signal selection |
0x40001B80 |
ACS_TEMP_SENSOR_CFG |
(1) DUTY_TEMP_SENS |
(1) DUTY_TEMP_SENS |
0x0 |
Duty cycling temperature sensor |
|
|
(0) ENABLE |
(0) ENABLE |
0x0 |
Internal temperature sensor enable |
0x40001B84 |
ACS_TEMP_CURR_CFG |
(19:16) CURRENT_VALUE |
(19:16) CURRENT_VALUE |
0x9 |
Temperature current value |
|
|
(13:8) CURRENT_TRIM |
(13:8) CURRENT_TRIM |
0x0 |
Temperature current trimming |
|
|
(7:4) GPIO_IN_USE |
(7:4) GPIO_IN_USE |
0x0 |
GPIO from which the duty cycle is used |
|
|
(1) DUTY_CURR |
(1) DUTY_CURR |
0x0 |
Duty cycling current enable |
|
|
(0) ENABLE |
(0) ENABLE |
0x0 |
Temperature current enable |
0x40001B88 |
ACS_GP_DATA |
(31:0) GP_DATA |
(31:0) GP_DATA |
0x0 |
32-bit General-Purpose RW Data |
0x40001B8C |
ACS_PWR_CTRL |
(27) SENSOR_PWR_EN |
(27) SENSOR_PWR_EN |
0x1 |
Sensor power control |
|
|
(26) SENSOR_ISOLATE |
(26) SENSOR_ISOLATE |
0x0 |
Sensor isolation control |
|
|
(25) CCAO_PWR_EN |
(25) CCAO_PWR_EN |
0x1 |
CryptoCell always on power control |
|
|
(24) CCAO_ISOLATE |
(24) CCAO_ISOLATE |
0x0 |
CryptoCell always on isolation control |
|
|
(23:0) POWER_KEY |
- |
N/A |
Write a key to enable the write to power controls |
0x40001B90 |
ACS_PWM_AO_CFG |
(15:8) HIGH |
(15:8) HIGH |
0x0 |
PWM high duty cycle |
|
|
(7:0) PERIOD |
(7:0) PERIOD |
0x0 |
PWM period |
0x40001B94 |
ACS_PWM_AO_CTRL |
- |
(8) ENABLE_STATUS |
0x0 |
Status of the PWM enable |
|
|
(2) RESET |
- |
N/A |
Reset the PWM |
|
|
(1) DISABLE |
- |
N/A |
Disable the PWM |
|
|
(0) ENABLE |
- |
N/A |
Enable the PWM |
0x40001B98 |
ACS_PWM_AO_COUNT |
- |
(7:0) COUNTER |
0x0 |
PWM counter |
0x40001B9C |
ACS_TEST |
- |
(23:16) JIC_BYTE0_RO |
0xFF |
JIC read only register bits (returning signals from analog part: tied to 1) |
|
|
- |
(9) DEBUG_ENABLE_FLAG |
0x0 |
Status flag of debug enable |
|
|
- |
(8) RTC_CLK_VALUE |
0x0 |
Value of RTC clock |
|
|
- |
(2) EN_TEST_PAD_STATUS |
0x0 |
EN_TEST pad state |
|
|
- |
(1) EN_TEST_CTRL_STATUS |
0x0 |
EN_TEST_CTRL state |
|
|
(0) EN_TEST_CTRL |
- |
N/A |
EN_TEST_CTRL can be written only one time |