CLK_SYS_CFG

Bit Field

Read/Write

Field Name

Description

19:16

RW

EXTCLK_PRESCALE

Prescale value for the input clock EXTCLK (1 to 16 in steps of 1)

11:8

RW

SWCLK_PRESCALE

Prescale value for the input clock from pad SWCLK (1 to 16 in steps of 1)

2:0

RW

SYSCLK_SRC_SEL

Controls the source of the system clock : SWCLK, RFCLK, RCCLK, or STANDBYCLK

Bit Field

Field Name

Value Symbol

Value Description

Hex Value

19:16

EXTCLK_PRESCALE

EXTCLK_PRESCALE_1

Divide by 1

0x0*

EXTCLK_PRESCALE_2

Divide by 2

0x1

EXTCLK_PRESCALE_4

Divide by 4

0x3

EXTCLK_PRESCALE_8

Divide by 8

0x7

EXTCLK_PRESCALE_15

Divide by 15

0xE

EXTCLK_PRESCALE_16

Divide by 16

0xF

11:8

SWCLK_PRESCALE

SWCLK_PRESCALE_1

Divide by 1

0x0*

SWCLK_PRESCALE_2

Divide by 2

0x1

SWCLK_PRESCALE_4

Divide by 4

0x3

SWCLK_PRESCALE_8

Divide by 8

0x7

SWCLK_PRESCALE_15

Divide by 15

0xE

SWCLK_PRESCALE_16

Divide by 16

0xF

2:0

SYSCLK_SRC_SEL

SYSCLK_CLKSRC_RCCLK

Select the RCCLK clock as SYSCLK clock source

0x0*

SYSCLK_CLKSRC_STANDBYCLK

Select the STANDBYCLK clock as SYSCLK clock source

0x1

SYSCLK_CLKSRC_RFCLK

Select the RFCLK clock as SYSCLK clock source

0x2

SYSCLK_CLKSRC_SWCLK

Select the SWCLK clock as SYSCLK clock source

0x3

SYSCLK_CLKSRC_EXTCLK

Select the EXTCLK clock asSYSCLK clock source

0x4