RF_DLL_CTRL
Bit Field |
Read/Write |
Field Name |
Description |
---|---|---|---|
31:29 |
RW |
RSSI_TUN_1_RSSI_TUN_GAIN |
RSSI tuning for gain |
28:24 |
RW |
RSSI_TUN_1_RSSI_ODD_OFFSET |
RSSI tuning for odd stages (offset to the even triangular wave) |
23:20 |
RW |
RSSI_TUN_1_RSSI_EVEN_MAX |
RSSI tuning for even stages (maximum value of the triangular wave) |
19:16 |
RW |
RSSI_TUN_1_RSSI_EVEN_MIN |
RSSI tuning for even stages (minimum value of the triangular wave) |
12 |
RW |
DLL_CTRL_CK_LAST_SEL_DELAY |
Last SEL delay |
11 |
RW |
DLL_CTRL_CK_FIRST_SEL_DELAY |
First SEL delay |
10 |
RW |
DLL_CTRL_CK_EXT_SEL |
Input clock selection |
9 |
RW |
DLL_CTRL_CK_DIG_EN |
Alternate ck_dig pin to output the PLL reference clock signal |
8 |
RW |
DLL_CTRL_CK_TEST_EN |
Output on GPIO the PLL reference clock signal via ck_test pin |
7 |
RW |
DLL_CTRL_TOO_FAST_ENB |
Lock range phase detector |
6 |
RW |
DLL_CTRL_LOCKED_DET_EN |
Reference frequency multiplier locked detector |
5 |
RW |
DLL_CTRL_LOCKED_AUTO_CHECK_EN |
Frequency multiplier is out of lock (usually because some input clocks from ck_xtal or ck_ext are missing) |
4 |
RW |
DLL_CTRL_FAST_ENB |
Disable fast mode locking of the reference frequency multiplier |
3:2 |
RW |
DLL_CTRL_CK_SEL_TX |
Selection of the clock used as frequency reference of the PLL in Tx mode (also to ck_test and ck_dig outputs) |
1:0 |
RW |
DLL_CTRL_CK_SEL_RX |
Selection of the clock used as frequency reference of the PLL in Rx mode (also to ck_test and ck_dig outputs) |
Bit Field |
Field Name |
Value Symbol |
Value Description |
Hex Value |
---|---|---|---|---|
31:29 |
RSSI_TUN_1_RSSI_TUN_GAIN |
RSSI_TUN_1_RSSI_TUN_GAIN_DEFAULT |
|
0x1* |
28:24 |
RSSI_TUN_1_RSSI_ODD_OFFSET |
RSSI_TUN_1_RSSI_ODD_OFFSET_DEFAULT |
|
0x4* |
23:20 |
RSSI_TUN_1_RSSI_EVEN_MAX |
RSSI_TUN_1_RSSI_EVEN_MAX_DEFAULT |
|
0x1* |
19:16 |
RSSI_TUN_1_RSSI_EVEN_MIN |
RSSI_TUN_1_RSSI_EVEN_MIN_DEFAULT |
|
0x1* |
12 |
DLL_CTRL_CK_LAST_SEL_DELAY |
DLL_CTRL_CK_LAST_SEL_DELAY_0 |
|
0x0* |
|
|
DLL_CTRL_CK_LAST_SEL_DELAY_1 |
|
0x1 |
11 |
DLL_CTRL_CK_FIRST_SEL_DELAY |
DLL_CTRL_CK_FIRST_SEL_DELAY_0 |
|
0x0* |
|
|
DLL_CTRL_CK_FIRST_SEL_DELAY_1 |
|
0x1 |
10 |
DLL_CTRL_CK_EXT_SEL |
DLL_CTRL_CK_EXT_SEL_XTAL |
Input clock comes from ck_xtal pin |
0x0* |
|
|
DLL_CTRL_CK_EXT_SEL_EXT |
Input clock comes from ck_ext pin |
0x1 |
9 |
DLL_CTRL_CK_DIG_EN |
DLL_CTRL_CK_DIG_EN_NOMINAL |
Don't use the alternate ck_dig pin to output the PLL reference clock signal |
0x0* |
|
|
DLL_CTRL_CK_DIG_EN_ALTERNATE |
Use the alternate ck_dig pin to output the PLL reference clock signal |
0x1 |
8 |
DLL_CTRL_CK_TEST_EN |
DLL_CTRL_CK_TEST_EN_0 |
Don't output on GPIO the PLL reference clock signal via ck_test pin |
0x0* |
|
|
DLL_CTRL_CK_TEST_EN_ENABLE |
Output on GPIO the PLL reference clock signal via ck_test pin |
0x1 |
7 |
DLL_CTRL_TOO_FAST_ENB |
DLL_CTRL_TOO_FAST_ENB_DISABLE |
Enable auxiliary wide lock range phase detector when fast mode locking is enabled (fast_enb = 0) |
0x0* |
|
|
DLL_CTRL_TOO_FAST_ENB_ENABLE |
The narrow lock range phase detector is enabled and bit 2 (fast_enb) must be high to avoid false frequency lock (slow mode locking) |
0x1 |
6 |
DLL_CTRL_LOCKED_DET_EN |
DLL_CTRL_LOCKED_DET_EN_DISABLE |
Disable reference frequency multiplier locked detector |
0x0 |
|
|
DLL_CTRL_LOCKED_DET_EN_ENABLE |
Enable reference frequency multiplier locked detector |
0x1* |
5 |
DLL_CTRL_LOCKED_AUTO_CHECK_EN |
DLL_CTRL_LOCKED_AUTO_CHECK_EN_DISABLE |
Manual reset should be performed via dll_rstb input(see Table 3) to relock the frequency multiplier |
0x0 |
|
|
DLL_CTRL_LOCKED_AUTO_CHECK_EN_ENABLE |
Frequency multiplier will try to lock again automatically |
0x1* |
4 |
DLL_CTRL_FAST_ENB |
DLL_CTRL_FAST_ENB_ENABLE |
Fast mode locking of the reference frequency multiplier |
0x0* |
|
|
DLL_CTRL_FAST_ENB_DISABLE |
|
0x1 |
3:2 |
DLL_CTRL_CK_SEL_TX |
DLL_CTRL_CK_SEL_TX_0 |
ref = ck_xtal ot ck_ext (if bit 8 is high) |
0x0 |
|
|
DLL_CTRL_CK_SEL_TX_1 |
ref = same as ck_sel = 00 if dll_en = 0, otherwise frequency(ref) = 3x frequency(ck_xtal) or 3x frequency(ck_ext) (if bit 8 is high) |
0x1* |
|
|
DLL_CTRL_CK_SEL_TX_2 |
ref = same as ck_sel = 01 but output frequency divided by 2 (used in normal RX mode when dll_en = 0) |
0x2 |
|
|
DLL_CTRL_CK_SEL_TX_3 |
ref = same as ck_sel = 01 but output frequency divided by 5 (used for RX mode with external signal at 132 MHz when dll_en = 0) |
0x3 |
1:0 |
DLL_CTRL_CK_SEL_RX |
DLL_CTRL_CK_SEL_RX_0 |
ref = ck_xtal ot ck_ext (if bit 8 is high) |
0x0* |
|
|
DLL_CTRL_CK_SEL_RX_1 |
ref = same as ck_sel = 00 if dll_en = 0, otherwise frequency(ref) = 3x frequency(ck_xtal) or 3x frequency(ck_ext) (if bit 8 is high) |
0x1 |
|
|
DLL_CTRL_CK_SEL_RX_2 |
ref = same as ck_sel = 01 but output frequency divided by 2 (used in normal RX mode when dll_en = 0) |
0x2 |
|
|
DLL_CTRL_CK_SEL_RX_3 |
ref = same as ck_sel = 01 but output frequency divided by 5 (used for RX mode with external signal at 132 MHz when dll_en = 0) |
0x3 |