SPI Interface
Address |
Register Name |
Register Write |
Register Read |
Default |
Description |
---|---|---|---|---|---|
0x40000B00 |
SPI0_CFG |
(23) TX_DMA_ENABLE |
(23) TX_DMA_ENABLE |
0x0 |
Enable/disable the TX DMA request |
|
|
(22) RX_DMA_ENABLE |
(22) RX_DMA_ENABLE |
0x0 |
Enable/disable the RX DMA request |
|
|
(21) TX_END_INT_ENABLE |
(21) TX_END_INT_ENABLE |
0x0 |
Enable/disable the TX interrupt |
|
|
(20) TX_START_INT_ENABLE |
(20) TX_START_INT_ENABLE |
0x0 |
Enable/disable the TX interrupt |
|
|
(19) RX_INT_ENABLE |
(19) RX_INT_ENABLE |
0x0 |
Enable/disable the RX interrupt |
|
|
(18) CS_RISE_INT_ENABLE |
(18) CS_RISE_INT_ENABLE |
0x0 |
Enable/disable the CS rise interrupt (slave mode only) |
|
|
(17) OVERRUN_INT_ENABLE |
(17) OVERRUN_INT_ENABLE |
0x0 |
Enable/disable the overrun interrupt |
|
|
(16) UNDERRUN_INT_ENABLE |
(16) UNDERRUN_INT_ENABLE |
0x0 |
Enable/disable the underrun interrupt |
|
|
(14:13) MODE |
(14:13) MODE |
0x0 |
Select the SPI master mode (ignored in slave mode) |
|
|
(12:8) WORD_SIZE |
(12:8) WORD_SIZE |
0x0 |
Select the SPI word size (word size = SPI_WORD_SIZE + 1) |
|
|
(7:4) PRESCALE |
(7:4) PRESCALE |
0x0 |
Prescale the SPI clock for master mode |
|
|
(2) CLK_PHASE |
(2) CLK_PHASE |
0x0 |
Select the SPI clock phase |
|
|
(1) CLK_POLARITY |
(1) CLK_POLARITY |
0x0 |
Select the SPI clock polarity |
|
|
(0) SLAVE |
(0) SLAVE |
0x0 |
Use the SPI interface as master or slave |
0x40000B04 |
SPI0_CTRL |
- |
(19) CS_STATUS |
0x1 |
SPI CS status |
|
|
- |
(18:17) MODE_STATUS |
0x0 |
SPI mode status |
|
|
- |
(16) ENABLE_STATUS |
0x0 |
SPI enable status |
|
|
(9) CS_0 |
- |
N/A |
Lower the SPI chip-select line (master mode) |
|
|
(8) CS_1 |
- |
N/A |
Raise the SPI chip-select line (master mode) |
|
|
(7) MODE_NOP |
- |
N/A |
Set mode to no operation |
|
|
(6) MODE_WRITE |
- |
N/A |
Set mode to read operation |
|
|
(5) MODE_READ |
- |
N/A |
Set mode to write operation |
|
|
(4) MODE_READ_WRITE |
- |
N/A |
Set mode to read and write operation |
|
|
(3) START |
- |
N/A |
Start a data transfer in master read mode |
|
|
(2) RESET |
- |
N/A |
Reset the SPI interface |
|
|
(1) DISABLE |
- |
N/A |
Disable the SPI interface |
|
|
(0) ENABLE |
- |
N/A |
Enable the SPI interface |
0x40000B08 |
SPI0_STATUS |
- |
(13) BUSY |
0x0 |
Indicate that the reception or transmission of the data is ongoing |
|
|
- |
(12) TX_REQ |
0x1 |
Indicate that TX data can be written |
|
|
- |
(11) RX_REQ |
0x0 |
Indicate that RX data can be read |
|
|
- |
(10) CS_RISE |
0x0 |
Indicate that CS has risen in slave mode |
|
|
- |
(9) OVERRUN |
0x0 |
Indicate that an overrun has occurred when receiving data on the SPI interface |
|
|
- |
(8) UNDERRUN |
0x0 |
Indicate that an underrun has occurred when transmitting data on the SPI interface |
|
|
(4) TX_REQ_SET |
- |
N/A |
Set TX_REQ status flag and clear internal TX buffer status |
|
|
(2) CS_RISE_CLEAR |
- |
N/A |
Clear the CS rise status flag |
|
|
(1) OVERRUN_CLEAR |
- |
N/A |
Clear the overrun status flag |
|
|
(0) UNDERRUN_CLEAR |
- |
N/A |
Clear the underrun status flag |
0x40000B0C |
SPI0_TX_DATA |
(31:0) TX_DATA |
(31:0) TX_DATA |
0x0 |
Single word buffer for data to be transmitted. When in master write or read_write mode, the transaction is started automatically |
0x40000B10 |
SPI0_RX_DATA |
- |
(31:0) RX_DATA |
0x0 |
Single word buffer for received data. When in master read mode, a new transaction is started automatically |
0x40000B14 |
SPI0_RX_DATA_NO_START |
- |
(31:0) RX_DATA |
0x0 |
Single word buffer for received data. Does not start a new transaction in master read mode, but does clear the RX_REQ flag |
0x40000B18 |
SPI0_RX_DATA_MIRROR |
- |
(31:0) RX_DATA |
0x0 |
Single word buffer for received data. Does not start a new transaction and does clear the RX_REQ flag |
0x40000BFC |
SPI0_ID_NUM |
- |
(19:16) SPI_NUMBER |
0x0 |
SPI Instance number |
|
|
- |
(15:8) SPI_MAJOR_REVISION |
0x2 |
SPI Major Revision number |
|
|
- |
(7:0) SPI_MINOR_REVISION |
0x0 |
SPI Minor Revision number |
0x40000C00 |
SPI1_CFG |
(23) TX_DMA_ENABLE |
(23) TX_DMA_ENABLE |
0x0 |
Enable/disable the TX DMA request |
|
|
(22) RX_DMA_ENABLE |
(22) RX_DMA_ENABLE |
0x0 |
Enable/disable the RX DMA request |
|
|
(21) TX_END_INT_ENABLE |
(21) TX_END_INT_ENABLE |
0x0 |
Enable/disable the TX interrupt |
|
|
(20) TX_START_INT_ENABLE |
(20) TX_START_INT_ENABLE |
0x0 |
Enable/disable the TX interrupt |
|
|
(19) RX_INT_ENABLE |
(19) RX_INT_ENABLE |
0x0 |
Enable/disable the RX interrupt |
|
|
(18) CS_RISE_INT_ENABLE |
(18) CS_RISE_INT_ENABLE |
0x0 |
Enable/disable the CS rise interrupt (slave mode only) |
|
|
(17) OVERRUN_INT_ENABLE |
(17) OVERRUN_INT_ENABLE |
0x0 |
Enable/disable the overrun interrupt |
|
|
(16) UNDERRUN_INT_ENABLE |
(16) UNDERRUN_INT_ENABLE |
0x0 |
Enable/disable the underrun interrupt |
|
|
(14:13) MODE |
(14:13) MODE |
0x0 |
Select the SPI master mode (ignored in slave mode) |
|
|
(12:8) WORD_SIZE |
(12:8) WORD_SIZE |
0x0 |
Select the SPI word size (word size = SPI_WORD_SIZE + 1) |
|
|
(7:4) PRESCALE |
(7:4) PRESCALE |
0x0 |
Prescale the SPI clock for master mode |
|
|
(2) CLK_PHASE |
(2) CLK_PHASE |
0x0 |
Select the SPI clock phase |
|
|
(1) CLK_POLARITY |
(1) CLK_POLARITY |
0x0 |
Select the SPI clock polarity |
|
|
(0) SLAVE |
(0) SLAVE |
0x0 |
Use the SPI interface as master or slave |
0x40000C04 |
SPI1_CTRL |
- |
(19) CS_STATUS |
0x1 |
SPI CS status |
|
|
- |
(18:17) MODE_STATUS |
0x0 |
SPI mode status |
|
|
- |
(16) ENABLE_STATUS |
0x0 |
SPI enable status |
|
|
(9) CS_0 |
- |
N/A |
Lower the SPI chip-select line (master mode) |
|
|
(8) CS_1 |
- |
N/A |
Raise the SPI chip-select line (master mode) |
|
|
(7) MODE_NOP |
- |
N/A |
Set mode to no operation |
|
|
(6) MODE_WRITE |
- |
N/A |
Set mode to read operation |
|
|
(5) MODE_READ |
- |
N/A |
Set mode to write operation |
|
|
(4) MODE_READ_WRITE |
- |
N/A |
Set mode to read and write operation |
|
|
(3) START |
- |
N/A |
Start a data transfer in master read mode |
|
|
(2) RESET |
- |
N/A |
Reset the SPI interface |
|
|
(1) DISABLE |
- |
N/A |
Disable the SPI interface |
|
|
(0) ENABLE |
- |
N/A |
Enable the SPI interface |
0x40000C08 |
SPI1_STATUS |
- |
(13) BUSY |
0x0 |
Indicate that the reception or transmission of the data is ongoing |
|
|
- |
(12) TX_REQ |
0x1 |
Indicate that TX data can be written |
|
|
- |
(11) RX_REQ |
0x0 |
Indicate that RX data can be read |
|
|
- |
(10) CS_RISE |
0x0 |
Indicate that CS has risen in slave mode |
|
|
- |
(9) OVERRUN |
0x0 |
Indicate that an overrun has occurred when receiving data on the SPI interface |
|
|
- |
(8) UNDERRUN |
0x0 |
Indicate that an underrun has occurred when transmitting data on the SPI interface |
|
|
(4) TX_REQ_SET |
- |
N/A |
Set TX_REQ status flag and clear internal TX buffer status |
|
|
(2) CS_RISE_CLEAR |
- |
N/A |
Clear the CS rise status flag |
|
|
(1) OVERRUN_CLEAR |
- |
N/A |
Clear the overrun status flag |
|
|
(0) UNDERRUN_CLEAR |
- |
N/A |
Clear the underrun status flag |
0x40000C0C |
SPI1_TX_DATA |
(31:0) TX_DATA |
(31:0) TX_DATA |
0x0 |
Single word buffer for data to be transmitted. When in master write or read_write mode, the transaction is started automatically |
0x40000C10 |
SPI1_RX_DATA |
- |
(31:0) RX_DATA |
0x0 |
Single word buffer for received data. When in master read mode, a new transaction is started automatically |
0x40000C14 |
SPI1_RX_DATA_NO_START |
- |
(31:0) RX_DATA |
0x0 |
Single word buffer for received data. Does not start a new transaction in master read mode, but does clear the RX_REQ flag |
0x40000C18 |
SPI1_RX_DATA_MIRROR |
- |
(31:0) RX_DATA |
0x0 |
Single word buffer for received data. Does not start a new transaction and does clear the RX_REQ flag |
0x40000CFC |
SPI1_ID_NUM |
- |
(19:16) SPI_NUMBER |
0x0 |
SPI Instance number |
|
|
- |
(15:8) SPI_MAJOR_REVISION |
0x2 |
SPI Major Revision number |
|
|
- |
(7:0) SPI_MINOR_REVISION |
0x0 |
SPI Minor Revision number |