RF_PLL_CTRL

Bit Field

Read/Write

Field Name

Description

26

RW

PLL_CTRL_DISABLE_CHP_SBS

Charge-pump disabling during sub-band selection (FLL and frequency ratios)

25

RW

PLL_CTRL_PLL_RX_48MEG

PLL frequency

24

RW

PLL_CTRL_SWCAP_TX_SAME_RX

Registers for Rx and Tx modes swcap in case of swcap_fsm=1

23

RW

PLL_CTRL_SWCAP_FSM

Selection of the swcap_fsm register

22

RW

PLL_CTRL_DLL_RSTB

Reset signal of the DLL (active low)

21:18

RW

PLL_CTRL_VCO_SUBBAND_TRIM

VCO sub-band selection bits

17

RW

PLL_CTRL_SUB_SEL_OFFS_EN

Add offset to sub-band selection comparator

16

RW

PLL_CTRL_DIV2_CLKVCO_TEST_EN

VCO signal divided by the programmable divider

15

RW

PLL_CTRL_VCODIV_CLK_TEST_EN

Output on GPIO the VCO signal divided by the programmable divider

13

RW

PLL_CTRL_CHP_DEAD_ZONE_EN

Charge-pump dead zone

12:11

RW

PLL_CTRL_CHP_CURR_OFF_TRIM_TX

Charge-pump offset current values selection bits in Tx mode

10:9

RW

PLL_CTRL_CHP_CURR_OFF_TRIM_RX

Charge-pump offset current values selection bits in Rx mode

8

RW

PLL_CTRL_HIGH_BW_FILTER_EN_TX

PLL filter high bandwidth needed in Tx mode

7

RW

PLL_CTRL_HIGH_BW_FILTER_EN_RX

PLL filter high bandwidth needed in Rx mode

6

RW

PLL_CTRL_FAST_CHP_EN_TX

High current output of the charge-pump for PLL Tx high bandwidth mode

5

RW

PLL_CTRL_FAST_CHP_EN_RX

High current output of the charge-pump for PLL Rx high bandwidth mode

4:3

RW

PLL_CTRL_CHP_MODE_TRIM

Select the frequency inside sub-band selection

2

RW

PLL_CTRL_CHP_CMC_EN

Common mode control block of the charge-pump

1

RW

PLL_CTRL_CHP_CURR_OFF_EN_TX

Charge-pump offset current in Tx mode

0

RW

PLL_CTRL_CHP_CURR_OFF_EN_RX

Charge-pump offset current in Rx mode

Bit Field

Field Name

Value Symbol

Value Description

Hex Value

26

PLL_CTRL_DISABLE_CHP_SBS

PLL_CTRL_2_DISABLE_CHP_SBS_DISABLE

Charge-pump is enabled during the sub-band selection

0x0*

PLL_CTRL_2_DISABLE_CHP_SBS_ENABLE

Charge-pump is disabled during the sub-band selection

0x1

25

PLL_CTRL_PLL_RX_48MEG

PLL_CTRL_2_PLL_RX_48MEG_24

PLL is set to 24MHz in Rx

0x0

PLL_CTRL_2_PLL_RX_48MEG_48

PLL is set to 48MHz in Rx

0x1*

24

PLL_CTRL_SWCAP_TX_SAME_RX

PLL_CTRL_2_SWCAP_TX_SAME_RX_DISABLE

The register for Rx and Tx swcap is not the same

0x0*

PLL_CTRL_2_SWCAP_TX_SAME_RX_ENABLE

The register for Rx and Tx swcap is the same

0x1

23

PLL_CTRL_SWCAP_FSM

PLL_CTRL_2_SWCAP_FSM_DISABLE

Don't use the swcap_fsm register as reference for the sub-band selection

0x0

PLL_CTRL_2_SWCAP_FSM_ENABLE

Use the swcap_fsm register as reference for the sub-band selection

0x1*

22

PLL_CTRL_DLL_RSTB

PLL_CTRL_2_DLL_RSTB_RESET

Reset the DLL

0x0

PLL_CTRL_2_DLL_RSTB_NO_RESET

Don't reset the DLL

0x1*

21:18

PLL_CTRL_VCO_SUBBAND_TRIM

PLL_CTRL_VCO_SUBBAND_TRIM_DEFAULT

0x0*

17

PLL_CTRL_SUB_SEL_OFFS_EN

PLL_CTRL_1_SUB_SEL_OFFS_EN_DISABLE

Don't add offset to sub-band selection comparator

0x0*

PLL_CTRL_1_SUB_SEL_OFFS_EN_ENABLE

Add offset to sub-band selection comparator

0x1

16

PLL_CTRL_DIV2_CLKVCO_TEST_EN

PLL_CTRL_1_DIV2_CLKVCO_TEST_EN_1

Division ratio set to 1

0x0*

PLL_CTRL_1_DIV2_CLKVCO_TEST_EN_2

Division ratio set to 2 (before to be outputted to ck_div_test)

0x1

15

PLL_CTRL_VCODIV_CLK_TEST_EN

PLL_CTRL_1_VCODIV_CLK_TEST_EN_DISABLE

Disable to output on GPIO the VCO signal divided by the programmable divider

0x0*

PLL_CTRL_ENABLE_VCODIV_CLK_TEST_EN_ENABLE

Enable to output on GPIO the VCO signal divided by the programmable divider

0x1

13

PLL_CTRL_CHP_DEAD_ZONE_EN

PLL_CTRL_1_CHP_DEAD_ZONE_EN_DISABLE

Disable charge-pump dead zone

0x0*

PLL_CTRL_ENABLE_CHP_DEAD_ZONE_EN_ENABLE

Enable charge-pump dead zone

0x1

12:11

PLL_CTRL_CHP_CURR_OFF_TRIM_TX

PLL_CTRL_1_CHP_CURR_OFF_TRIM_TX_15

d_phi=15

0x0

PLL_CTRL_1_CHP_CURR_OFF_TRIM_TX_22

d_phi=22.5

0x1

PLL_CTRL_1_CHP_CURR_OFF_TRIM_TX_30

d_phi = 30

0x2

PLL_CTRL_1_CHP_CURR_OFF_TRIM_TX_60

d_phi = 60

0x3*

10:9

PLL_CTRL_CHP_CURR_OFF_TRIM_RX

PLL_CTRL_1_CHP_CURR_OFF_TRIM_RX_15

d_phi=15

0x0

PLL_CTRL_1_CHP_CURR_OFF_TRIM_RX_22

d_phi=22.5

0x1

PLL_CTRL_1_CHP_CURR_OFF_TRIM_RX_30

d_phi = 30

0x2

PLL_CTRL_1_CHP_CURR_OFF_TRIM_RX_60

d_phi = 60

0x3*

8

PLL_CTRL_HIGH_BW_FILTER_EN_TX

PLL_CTRL_HIGH_BW_FILTER_EN_TX_DISABLE

Disable the PLL filter high bandwidth needed in TX

0x0

PLL_CTRL_HIGH_BW_FILTER_EN_TX_ENABLE

Enable the PLL filter high bandwidth needed in TX

0x1*

7

PLL_CTRL_HIGH_BW_FILTER_EN_RX

PLL_CTRL_HIGH_BW_FILTER_EN_RX_DISABLE

Disable the PLL filter high bandwidth needed in RX

0x0*

PLL_CTRL_HIGH_BW_FILTER_EN_RX_ENABLE

Enable the PLL filter high bandwidth needed in RX

0x1

6

PLL_CTRL_FAST_CHP_EN_TX

PLL_CTRL_FAST_CHP_EN_TX_DISABLE

Disable the high current output of the charge-pump in TX

0x0

PLL_CTRL_FAST_CHP_EN_TX_ENABLE

Enable the high current output of the charge-pum in TX

0x1*

5

PLL_CTRL_FAST_CHP_EN_RX

PLL_CTRL_FAST_CHP_EN_RX_DISABLE

Disable the high current output of the charge-pump in RX

0x0*

PLL_CTRL_FAST_CHP_EN_RX_ENABLE

Enable the high current output of the charge-pump in RX

0x1

4:3

PLL_CTRL_CHP_MODE_TRIM

PLL_CTRL_CHP_MODE_TRIM_MIN_FREQ

Minimum frequency inside sub-band selection

0x0*

PLL_CTRL_CHP_MODE_TRIM_MED_FREQ

Medium frequency inside sub-band selection

0x1

PLL_CTRL_CHP_MODE_TRIM_MAX_FREQ

Maximum frequency inside sub-band selection

0x2

2

PLL_CTRL_CHP_CMC_EN

PLL_CTRL_CHP_CMC_EN_DISABLE

Disable the common mode control block of the charge-pump

0x0

PLL_CTRL_CHP_CMC_EN_ENABLE

Enable the common mode control block of the charge-pump

0x1*

1

PLL_CTRL_CHP_CURR_OFF_EN_TX

PLL_CTRL_CHP_CURR_OFF_EN_TX_DISABLE

Disable the charge-pump offset current in TX

0x0

PLL_CTRL_CHP_CURR_OFF_EN_TX_ENABLE

Enable the charge-pump offset current in TX

0x1*

0

PLL_CTRL_CHP_CURR_OFF_EN_RX

PLL_CTRL_CHP_CURR_OFF_EN_RX_DISABLE

Disable the charge-pump offset current in RX

0x0*

PLL_CTRL_CHP_CURR_OFF_EN_RX_ENABLE

Enable the charge-pump offset current in RX

0x1