RF_REG33
Bit Field |
Read/Write |
Field Name |
Description |
---|---|---|---|
26:24 |
RW |
CK_DIV_1_6_CK_DIV_1_6 |
Clock division factor for ck_div_1_6 |
23:16 |
RW |
SPARES_SPARES |
Spare bits |
14 |
RW |
PADS_PE_DS_GPIO_DS |
Increased drive strength of the digital pads |
13 |
RW |
PADS_PE_DS_GPIO_PE |
Pull-up of the GPIO pads |
12 |
RW |
PADS_PE_DS_NRESET_PE |
Pull-up of the NRESET pads |
11 |
RW |
PADS_PE_DS_SPI_MISO_PE |
Pull-up of the SPI MISO pads |
10 |
RW |
PADS_PE_DS_SPI_MOSI_PE |
Pull-up of the SPI MOSI pads |
9 |
RW |
PADS_PE_DS_SPI_SCLK_PE |
Pull-up of the SPI CLK pads |
8 |
RW |
PADS_PE_DS_SPI_CS_N_PE |
Pull-up of the SPI CSN pads |
7:6 |
RW |
SUBBAND_FLL_SB_FLL_DITHER |
Select the dithering |
5:4 |
RW |
SUBBAND_FLL_SB_FLL_CIC_TAU |
Set the CIC decimator factor |
3 |
RW |
SUBBAND_FLL_SB_FLL_PH_4_N8 |
Phases in the frequency detector |
2:0 |
RW |
SUBBAND_FLL_SB_FLL_WAIT |
Set the number of CIC samples before stopping the FLL |
Bit Field |
Field Name |
Value Symbol |
Value Description |
Hex Value |
---|---|---|---|---|
26:24 |
CK_DIV_1_6_CK_DIV_1_6 |
CK_DIV_1_6_NO_CLOCK |
No clock is generated |
0x0* |
|
|
CK_DIV_1_6_PRESCALE_1 |
|
0x1 |
|
|
CK_DIV_1_6_PRESCALE_2 |
|
0x2 |
|
|
CK_DIV_1_6_PRESCALE_3 |
|
0x3 |
|
|
CK_DIV_1_6_PRESCALE_4 |
|
0x4 |
|
|
CK_DIV_1_6_PRESCALE_5 |
|
0x5 |
|
|
CK_DIV_1_6_PRESCALE_6 |
|
0x6 |
|
|
CK_DIV_1_6_PRESCALE_7 |
|
0x7 |
14 |
PADS_PE_DS_GPIO_DS |
PADS_PE_DS_GPIO_DS_DISABLE |
Disable the increased drive strength of the digital pads |
0x0* |
|
|
PADS_PE_DS_GPIO_DS_ENABLE |
Enable the increased drive strength of the digital pads |
0x1 |
13 |
PADS_PE_DS_GPIO_PE |
PADS_PE_DS_GPIO_PE_DISABLE |
Disable the pull-up of the GPIO pads |
0x0* |
|
|
PADS_PE_DS_GPIO_PE_ENABLE |
Enable the pull-up of the GPIO pads |
0x1 |
12 |
PADS_PE_DS_NRESET_PE |
PADS_PE_DS_NRESET_PE_DISABLE |
Disable the pull-up of the NRESET pads |
0x0* |
|
|
PADS_PE_DS_NRESET_PE_ENABLE |
Enable the pull-up of the NRESET pads |
0x1 |
11 |
PADS_PE_DS_SPI_MISO_PE |
PADS_PE_DS_SPI_MISO_PE_DISABLE |
Disable the pull-up of the SPI MISO pads |
0x0* |
|
|
PADS_PE_DS_SPI_MISO_PE_ENABLE |
Enable the pull-up of the SPI MISO pads |
0x1 |
10 |
PADS_PE_DS_SPI_MOSI_PE |
PADS_PE_DS_SPI_MOSI_PE_DISABLE |
Disable the pull-up of the SPI MOSI pads |
0x0* |
|
|
PADS_PE_DS_SPI_MOSI_PE_ENABLE |
Enable the pull-up of the SPI MOSI pads |
0x1 |
9 |
PADS_PE_DS_SPI_SCLK_PE |
PADS_PE_DS_SPI_SCLK_PE_DISABLE |
Disable the pull-up of the SPI CLK pads |
0x0* |
|
|
PADS_PE_DS_SPI_SCLK_PE_ENABLE |
Enable the pull-up of the SPI CLK pads |
0x1 |
8 |
PADS_PE_DS_SPI_CS_N_PE |
PADS_PE_DS_SPI_CS_N_PE_DISABLE |
Disable the pull-up of the SPI CSN pads |
0x0* |
|
|
PADS_PE_DS_SPI_CS_N_PE_ENABLE |
Enable the pull-up of the SPI CSN pads |
0x1 |
7:6 |
SUBBAND_FLL_SB_FLL_DITHER |
SUBBAND_FLL_SB_FLL_DITHER_OFF |
No dithering |
0x0* |
|
|
SUBBAND_FLL_SB_FLL_DITHER_PN9 |
PN9 positive |
0x1 |
|
|
SUBBAND_FLL_SB_FLL_DITHER_PN10 |
PN10 negative |
0x2 |
|
|
SUBBAND_FLL_SB_FLL_DITHER_PN9_PN10 |
PN9+PN10 |
0x3 |
5:4 |
SUBBAND_FLL_SB_FLL_CIC_TAU |
SUBBAND_FLL_SB_FLL_CIC_TAU_16 |
Decimate by 16 |
0x0 |
|
|
SUBBAND_FLL_SB_FLL_CIC_TAU_32 |
Decimate by 32 |
0x1 |
|
|
SUBBAND_FLL_SB_FLL_CIC_TAU_64 |
Decimate by 64 |
0x2 |
|
|
SUBBAND_FLL_SB_FLL_CIC_TAU_128 |
Decimate by 128 |
0x3* |
3 |
SUBBAND_FLL_SB_FLL_PH_4_N8 |
SUBBAND_FLL_SB_FLL_PH_4_N8_8 |
Use 8 phases in the frequency detector |
0x0* |
|
|
SUBBAND_FLL_SB_FLL_PH_4_N8_4 |
Use 4 phases in the frequency detector |
0x1 |
2:0 |
SUBBAND_FLL_SB_FLL_WAIT |
SUBBAND_FLL_SB_FLL_WAIT_DEFAULT |
|
0x3* |