RF Front-End 2.4 GHz

Address

Register Name

Register Write

Register Read

Default

Description

0x40040800

RF0_REG00

(31) DATAWHITE_BTLE_DW_BTLE

(31) DATAWHITE_BTLE_DW_BTLE

0x1

Data whitening control

(30:24) DATAWHITE_BTLE_DW_BTLE_RST

(30:24) DATAWHITE_BTLE_DW_BTLE_RST

0x0

Reset value to put on the Bluetooth LE data whitening shift register

(23) FOURFSK_CODING_EN_FOURFSK_CODING

(23) FOURFSK_CODING_EN_FOURFSK_CODING

0x0

Enable 4FSK coding

(22:20) FOURFSK_CODING_TX_FOURFSK_CODING

(22:20) FOURFSK_CODING_TX_FOURFSK_CODING

0x0

Set the 4FSK coding (Tx mode)

(18:16) FOURFSK_CODING_RX_FOURFSK_CODING

(18:16) FOURFSK_CODING_RX_FOURFSK_CODING

0x0

Set the 4FSK decoding (Rx mode)

(14) MODE2_DIFF_CODING

(14) MODE2_DIFF_CODING

0x0

Differential coding/decoding

(13) MODE2_PSK_NFSK

(13) MODE2_PSK_NFSK

0x0

FSK/PSK mode selection

(12:8) MODE2_TESTMODE

(12:8) MODE2_TESTMODE

0x0

Output test mode

(7) MODE_NOT_TO_IDLE

(7) MODE_NOT_TO_IDLE

0x0

FSM goes in suspend mode after a Tx or Rx packet

(5) MODE_EN_FSM

(5) MODE_EN_FSM

0x1

Radio FSM control

(4) MODE_EN_DESERIALIZER

(4) MODE_EN_DESERIALIZER

0x0

Deserializer control

(3) MODE_EN_SERIALIZER

(3) MODE_EN_SERIALIZER

0x0

Serializer control

(2) MODE_TX_NRX

(2) MODE_TX_NRX

0x0

Select Tx or Rx mode

(1:0) MODE_MODE

(1:0) MODE_MODE

0x2

Select the working mode of the digital baseband

0x40040804

RF0_REG01

(31:24) TAU_PHASE_RECOV_TAU_PHASE_RECOV

(31:24) TAU_PHASE_RECOV_TAU_PHASE_RECOV

0x14

Time constant of the fine carrier recovery block (banked)

(23:16) TAU_ROUGH_RECOV_TAU_ROUGH_RECOV

(23:16) TAU_ROUGH_RECOV_TAU_ROUGH_RECOV

0xB

Time constant of the rough carrier recovery block (banked)

(15) CARRIER_RECOVERY_EN_CORRECT_CFREQ_AFC

(15) CARRIER_RECOVERY_EN_CORRECT_CFREQ_AFC

0x0

Automatic AFC correction (banked)

(14) CARRIER_RECOVERY_CORRECT_CFREQ_IF_NEG

(14) CARRIER_RECOVERY_CORRECT_CFREQ_IF_NEG

0x0

IF correction (banked)

(13) CARRIER_RECOVERY_EN_CORRECT_CFREQ_IF

(13) CARRIER_RECOVERY_EN_CORRECT_CFREQ_IF

0x1

Automatic IF correction (banked)

(12) CARRIER_RECOVERY_AFC_NEG

(12) CARRIER_RECOVERY_AFC_NEG

0x0

AFC correction (banked)

(11) CARRIER_RECOVERY_STARTER_MODE

(11) CARRIER_RECOVERY_STARTER_MODE

0x0

Starter mode (banked)

(10) CARRIER_RECOVERY_EN_AFC

(10) CARRIER_RECOVERY_EN_AFC

0x0

Automatic frequency control (banked)

(9) CARRIER_RECOVERY_EN_FINE_RECOV

(9) CARRIER_RECOVERY_EN_FINE_RECOV

0x1

Fine carrier recovery (banked)

(8) CARRIER_RECOVERY_EN_ROUGH_RECOV

(8) CARRIER_RECOVERY_EN_ROUGH_RECOV

0x0

Rough carrier recovery (banked)

(6) MOD_TX_PULSE_NSYM

(6) MOD_TX_PULSE_NSYM

0x0

Tx pulse shape function

(5) MOD_TX_EN_INTERP

(5) MOD_TX_EN_INTERP

0x0

Tx CIC interpolator

(4:0) MOD_TX_CK_TX_M

(4:0) MOD_TX_CK_TX_M

0x0

Unsigned value determining the Tx CIC interpolator frequency

0x40040808

RF0_REG02

(25:24) DATARATE_OFFSET_DR_LIMIT

(25:24) DATARATE_OFFSET_DR_LIMIT

0x0

Set the data-rate recovery limits

(23:16) DATARATE_OFFSET_DATARATE_OFFSET

(23:16) DATARATE_OFFSET_DATARATE_OFFSET

0x0

Data-rate offset

(15:8) TAU_DATARATE_RECOV_TAU_DATARATE_RECOV

(15:8) TAU_DATARATE_RECOV_TAU_DATARATE_RECOV

0x20

Time constant of the data-rate recovery

(7:0) TAU_CLK_RECOV_TAU_CLK_RECOV

(7:0) TAU_CLK_RECOV_TAU_CLK_RECOV

0x9

Time constant of the clock recovery (banked)

0x4004080C

RF0_REG03

(31:30) MAC_CONF_MAC_TIMER_GR

(31:30) MAC_CONF_MAC_TIMER_GR

0x2

MAC timer granularity

(29) MAC_CONF_RX_MAC_ACT

(29) MAC_CONF_RX_MAC_ACT

0x0

Switch FSM to Rx or Tx mode after an Rx mode

(28) MAC_CONF_RX_MAC_TX_NRX

(28) MAC_CONF_RX_MAC_TX_NRX

0x0

Switch FSM to Tx mode after an Rx mode (Rx otherwise)

(27) MAC_CONF_RX_MAC_START_NSTOP

(27) MAC_CONF_RX_MAC_START_NSTOP

0x0

MAC timer activation after sync word detection

(26) MAC_CONF_TX_MAC_ACT

(26) MAC_CONF_TX_MAC_ACT

0x0

Switch FSM to Rx or Tx mode after a Tx mode

(25) MAC_CONF_TX_MAC_TX_NRX

(25) MAC_CONF_TX_MAC_TX_NRX

0x0

Switch FSM to Tx mode after a Tx mode (Rx otherwise)

(24) MAC_CONF_TX_MAC_START_NSTOP

(24) MAC_CONF_TX_MAC_START_NSTOP

0x0

MAC timer activation after packet transmission

(23) IRQ_CONF_IRQ_HIGH_Z

(23) IRQ_CONF_IRQ_HIGH_Z

0x0

Pads are set to high-Z when the IRQ is not active

(22) IRQ_CONF_IRQ_ACTIVE_LOW

(22) IRQ_CONF_IRQ_ACTIVE_LOW

0x1

IRQ are active low

(21:16) IRQ_CONF_IRQS_MASK

(21:16) IRQ_CONF_IRQS_MASK

0x0

Mask to determine which IRQs are enabled (active high)

(15:13) FIFO_2_FIFO_THR_TX

(15:13) FIFO_2_FIFO_THR_TX

0x0

Threshold indicating the "almost empty" Tx FIFO state

(12) FIFO_2_WAIT_TXFIFO_WR

(12) FIFO_2_WAIT_TXFIFO_WR

0x0

FSM will wait a Tx FIFO write before starting the Tx mode in case of an empty Tx FIFO

(11) FIFO_2_STOP_ON_RXFF_OVFLW

(11) FIFO_2_STOP_ON_RXFF_OVFLW

0x0

Stop the reception in case of a FIFO overflow

(10) FIFO_2_STOP_ON_TXFF_UNFLW

(10) FIFO_2_STOP_ON_TXFF_UNFLW

0x0

Stop the transmission in case of a FIFO underflow

(9) FIFO_2_RXFF_FLUSH_ON_START

(9) FIFO_2_RXFF_FLUSH_ON_START

0x1

Flush the Rx FIFO when the Rx mode is enabled in order to receive a packet with an empty FIFO

(8) FIFO_2_TXFF_FLUSH_ON_STOP

(8) FIFO_2_TXFF_FLUSH_ON_STOP

0x1

Flush the Tx FIFO after the end of a packet transmission in order to have an empty FIFO

(7) FIFO_FIFO_FLUSH_ON_OVFLW

(7) FIFO_FIFO_FLUSH_ON_OVFLW

0x0

Overflow FIFO flush control

(6) FIFO_FIFO_FLUSH_ON_ADDR_ERR

(6) FIFO_FIFO_FLUSH_ON_ADDR_ERR

0x0

Address error FIFO flush control

(5) FIFO_FIFO_FLUSH_ON_PL_ERR

(5) FIFO_FIFO_FLUSH_ON_PL_ERR

0x0

Packet length error FIFO flush control

(4) FIFO_FIFO_FLUSH_ON_CRC_ERR

(4) FIFO_FIFO_FLUSH_ON_CRC_ERR

0x1

CRC error FIFO flush control

(3) FIFO_RX_FIFO_ACK

(3) FIFO_RX_FIFO_ACK

0x0

Rx FIFO acknowledgement

(2:0) FIFO_FIFO_THR

(2:0) FIFO_FIFO_THR

0x0

Threshold indicating the "almost full" Rx FIFO state

0x40040810

RF0_PADS_03

(28:24) PAD_CONF_1_PAD_3_CONF

(28:24) PAD_CONF_1_PAD_3_CONF

0x0

Configuration of GPIO pad 3

(20:16) PAD_CONF_1_PAD_2_CONF

(20:16) PAD_CONF_1_PAD_2_CONF

0x0

Configuration of GPIO pad 2

(12:8) PAD_CONF_1_PAD_1_CONF

(12:8) PAD_CONF_1_PAD_1_CONF

0x0

Configuration of GPIO pad 1

(4:0) PAD_CONF_1_PAD_0_CONF

(4:0) PAD_CONF_1_PAD_0_CONF

0x0

Configuration of GPIO pad 0

0x40040814

RF0_PADS_47

(28:24) PAD_CONF_2_PAD_7_CONF

(28:24) PAD_CONF_2_PAD_7_CONF

0x0

Configuration of GPIO pad 7

(20:16) PAD_CONF_2_PAD_6_CONF

(20:16) PAD_CONF_2_PAD_6_CONF

0x0

Configuration of GPIO pad 6

(12:8) PAD_CONF_2_PAD_5_CONF

(12:8) PAD_CONF_2_PAD_5_CONF

0x0

Configuration of GPIO pad 5

(4:0) PAD_CONF_2_PAD_4_CONF

(4:0) PAD_CONF_2_PAD_4_CONF

0x0

Configuration of GPIO pad 4

0x40040818

RF0_CENTER_FREQ

(31) CENTER_FREQ_ADAPT_CFREQ

(31) CENTER_FREQ_ADAPT_CFREQ

0x1

Frequency adaptation between Tx and Rx modes

(30) CENTER_FREQ_RX_DIV_5_N6

(30) CENTER_FREQ_RX_DIV_5_N6

0x0

Ratio of the PLL reference between Tx and Rx modes

(29:0) CENTER_FREQ_CENTER_FREQUENCY

(29:0) CENTER_FREQ_CENTER_FREQUENCY

0x215C71B

Set the center frequency

0x4004081C

RF0_PADS_89

(31:24) TX_MAC_TIMER_TX_MAC_TIMER

(31:24) TX_MAC_TIMER_TX_MAC_TIMER

0x82

Time to wait after the Tx mode

(23:16) RX_MAC_TIMER_RX_MAC_TIMER

(23:16) RX_MAC_TIMER_RX_MAC_TIMER

0x23

Time to wait after the Rx mode

(12:8) PAD_CONF_3_PAD_9_CONF

(12:8) PAD_CONF_3_PAD_9_CONF

0x0

Configuration of GPIO pad 9

(4:0) PAD_CONF_3_PAD_8_CONF

(4:0) PAD_CONF_3_PAD_8_CONF

0x0

Configuration of GPIO pad 8

0x40040820

RF0_REG08

(31:30) MOD_INFO_RX_DIV_CK_RX

(31:30) MOD_INFO_RX_DIV_CK_RX

0x0

Set the clock divider for the Rx mode (banked)

(29) MOD_INFO_RX_SYMBOL_2BIT_RX

(29) MOD_INFO_RX_SYMBOL_2BIT_RX

0x0

Rx symbol bits composition (banked)

(28:24) MOD_INFO_RX_DR_M_RX

(28:24) MOD_INFO_RX_DR_M_RX

0x0

Unsigned value determining the oversampling frequency and consequently the data-rate (banked)

(23:22) MOD_INFO_TX_DIV_CK_TX

(23:22) MOD_INFO_TX_DIV_CK_TX

0x0

Set the clock divider for the Tx mode (banked)

(21) MOD_INFO_TX_SYMBOL_2BIT_TX

(21) MOD_INFO_TX_SYMBOL_2BIT_TX

0x0

Tx symbol bits composition (banked)

(20:16) MOD_INFO_TX_DR_M_TX

(20:16) MOD_INFO_TX_DR_M_TX

0x0

Unsigned value determining the oversampling frequency and consequently the data-rate (banked)

(14) CHANNEL_SWITCH_IQ

(14) CHANNEL_SWITCH_IQ

0x0

Switch I and Q channels

(13:8) CHANNEL_CHANNEL

(13:8) CHANNEL_CHANNEL

0x0

Channel number

(3) BANK_DATARATE_TX_NRX

(3) BANK_DATARATE_TX_NRX

0x0

Select the data-rate register

(2) BANK_STD_BLE_RATES

(2) BANK_STD_BLE_RATES

0x0

Select the actual bank behavior

(1:0) BANK_BANK

(1:0) BANK_BANK

0x0

Select the used bank

0x40040824

RF0_CODING

(31) CODING_EN_DATAWHITE

(31) CODING_EN_DATAWHITE

0x1

Data-whitening enabling (banked)

(30) CODING_I_NQ_DELAYED

(30) CODING_I_NQ_DELAYED

0x0

Channel I delay (banked)

(29) CODING_OFFSET

(29) CODING_OFFSET

0x0

Offset (delay) introduction (banked)

(28) CODING_BIT_INVERT

(28) CODING_BIT_INVERT

0x0

Bit value inversion in Tx and Rx modes (banked)

(27) CODING_EVEN_BEFORE_ODD

(27) CODING_EVEN_BEFORE_ODD

0x0

Determine the bit order in case of a 2 bits per symbol modulation (banked)

(26) CODING_EN_802154_L2F

(26) CODING_EN_802154_L2F

0x0

Linear to frequency encoding needed in order to modulate an OQPSK as an MSK (banked)

(25) CODING_EN_802154_B2C

(25) CODING_EN_802154_B2C

0x0

Bit to chips encoding used in the IEEE 802.15.4 standard (banked)

(24) CODING_EN_MANCHESTER

(24) CODING_EN_MANCHESTER

0x0

Manchester encoding (banked)

(23) CHANNELS_2_EN_CHANNEL_SEL

(23) CHANNELS_2_EN_CHANNEL_SEL

0x1

Definition of channels (banked)

(22) CHANNELS_2_EN_CHN_BLE

(22) CHANNELS_2_EN_CHN_BLE

0x1

BLE channels index LUT (banked)

(19:16) CHANNELS_2_CHANNEL_SPACING_HI

(19:16) CHANNELS_2_CHANNEL_SPACING_HI

0x7

Channel spacing MSB (banked)

(15:0) CHANNELS_1_CHANNEL_SPACING_LO

(15:0) CHANNELS_1_CHANNEL_SPACING_LO

0x1C72

Channel spacing LSB (banked)

0x40040828

RF0_PACKET_HANDLING

(31:24) PREAMBLE_PREAMBLE

(31:24) PREAMBLE_PREAMBLE

0x55

Preamble to be inserted (banked)

(22) PACKET_LENGTH_OPTS_EN_PACKET_LEN_FIX

(22) PACKET_LENGTH_OPTS_EN_PACKET_LEN_FIX

0x0

Packet length configuration (banked)

(21:18) PACKET_LENGTH_OPTS_PACKET_LEN_CORR

(21:18) PACKET_LENGTH_OPTS_PACKET_LEN_CORR

0x0

Signed value specifying the correction to apply to the specified packet length (banked)

(17:16) PACKET_LENGTH_OPTS_PACKET_LEN_POS

(17:16) PACKET_LENGTH_OPTS_PACKET_LEN_POS

0x1

Unsigned value that specifies the position of the packet length after the pattern (banked)

(15:8) PACKET_LENGTH_PACKET_LEN

(15:8) PACKET_LENGTH_PACKET_LEN

0xFF

The packet length in the fixed packet length mode (banked)

(7) PACKET_HANDLING_LSB_FIRST

(7) PACKET_HANDLING_LSB_FIRST

0x1

Select LSB or MSB to send first (banked)

(6) PACKET_HANDLING_EN_CRC

(6) PACKET_HANDLING_EN_CRC

0x1

Automatic CRC evaluation and insertion (banked)

(5) PACKET_HANDLING_EN_CRC_ON_PKTLEN

(5) PACKET_HANDLING_EN_CRC_ON_PKTLEN

0x1

CRC calculation on the packet length part of the packet (banked)

(4) PACKET_HANDLING_EN_PREAMBLE

(4) PACKET_HANDLING_EN_PREAMBLE

0x1

Automatic preamble insertion (banked)

(3) PACKET_HANDLING_EN_MULTI_FRAME

(3) PACKET_HANDLING_EN_MULTI_FRAME

0x0

Multi-frame packet (banked)

(2) PACKET_HANDLING_ENB_DW_ON_CRC

(2) PACKET_HANDLING_ENB_DW_ON_CRC

0x0

Data-whitening on the CRC disabling (banked)

(1) PACKET_HANDLING_EN_PATTERN

(1) PACKET_HANDLING_EN_PATTERN

0x1

Automatic pattern insertion and recognition (banked)

(0) PACKET_HANDLING_EN_PACKET

(0) PACKET_HANDLING_EN_PACKET

0x1

Packet handler enabling (banked)

0x4004082C

RF0_SYNC_PATTERN

(31:0) PATTERN

(31:0) PATTERN

0x8E89BED6

Pattern (sync word) to be inserted or recognized (banked)

0x40040830

RF0_REG0C

(31:16) ADDRESS_ADDRESS

(31:16) ADDRESS_ADDRESS

0x0

Address of the node (banked)

(11) ADDRESS_CONF_ADDRESS_LEN

(11) ADDRESS_CONF_ADDRESS_LEN

0x0

Address length selection (banked)

(10) ADDRESS_CONF_EN_ADDRESS_RX_BR

(10) ADDRESS_CONF_EN_ADDRESS_RX_BR

0x0

Broadcast address detection in Rx mode (banked)

(9) ADDRESS_CONF_EN_ADDRESS_RX

(9) ADDRESS_CONF_EN_ADDRESS_RX

0x0

Address detection in Rx mode (banked)

(8) ADDRESS_CONF_EN_ADDRESS_TX

(8) ADDRESS_CONF_EN_ADDRESS_TX

0x0

Address insertion in Tx mode (banked)

(7:0) PREAMBLE_LENGTH_PREAMBLE_LEN

(7:0) PREAMBLE_LENGTH_PREAMBLE_LEN

0x0

Length of the preamble -1 (banked)

0x40040834

RF0_PACKET_EXTRA

(29:28) CONV_CODES_CONF_STOP_WORD_LEN

(29:28) CONV_CODES_CONF_STOP_WORD_LEN

0x0

Length of the stop word (banked)

(27:26) CONV_CODES_CONF_CC_VITERBI_LEN

(27:26) CONV_CODES_CONF_CC_VITERBI_LEN

0x2

Set the memory length of the Viterbi decoder (banked)

(25) CONV_CODES_CONF_CC_EN_TX_STOP

(25) CONV_CODES_CONF_CC_EN_TX_STOP

0x0

Stop word at the end of the transmission (banked)

(24) CONV_CODES_CONF_EN_CONV_CODE

(24) CONV_CODES_CONF_EN_CONV_CODE

0x0

Convolutional codes (banked)

(22) PACKET_EXTRA_FIFO_REWIND

(22) PACKET_EXTRA_FIFO_REWIND

0x0

Rewind the FIFO to the initial stage at the end of a Tx transmission (banked)

(21) PACKET_EXTRA_BLE_PREAMBLE

(21) PACKET_EXTRA_BLE_PREAMBLE

0x1

Handle the preamble directly in Tx mode (PREAMBLE register is not used) according to the BLE standard (banked)

(20) PACKET_EXTRA_PKT_INFO_PRE_NPOST

(20) PACKET_EXTRA_PKT_INFO_PRE_NPOST

0x0

Packet information sampling (banked)

(19:18) PACKET_EXTRA_PATTERN_MAX_ERR

(19:18) PACKET_EXTRA_PATTERN_MAX_ERR

0x0

Unsigned value that specifies the maximum number of errors in the pattern recognition (banked)

(17:16) PACKET_EXTRA_PATTERN_WORD_LEN

(17:16) PACKET_EXTRA_PATTERN_WORD_LEN

0x3

Pattern word length (banked)

(15:0) ADDRESS_BROADCAST_ADDRESS_BR

(15:0) ADDRESS_BROADCAST_ADDRESS_BR

0x0

Broadcast address (banked)

0x40040838

RF0_CRC_POLYNOMIAL

(31:0) CRC_POLY

(31:0) CRC_POLY

0x80032D

CRC polynomial (banked)

0x4004083C

RF0_CRC_RST

(31:0) CRC_RST

(31:0) CRC_RST

0x555555

CRC reset value (banked)

0x40040840

RF0_REG10

(25:21) CONV_CODES_PUNCT_CC_PUNCT_1

(25:21) CONV_CODES_PUNCT_CC_PUNCT_1

0x1

Puncture of the second convolutional code (banked)

(20:16) CONV_CODES_PUNCT_CC_PUNCT_0

(20:16) CONV_CODES_PUNCT_CC_PUNCT_0

0x1

Puncture of the first convolutional code (banked)

(11) FRAC_CONF_TX_FRAC_GAIN

(11) FRAC_CONF_TX_FRAC_GAIN

0x0

Additional gain for fractional data-rates in Tx mode (banked)

(10) FRAC_CONF_RX_FRAC_GAIN

(10) FRAC_CONF_RX_FRAC_GAIN

0x0

Additional gain for fractional data-rates in Rx mode (banked)

(9) FRAC_CONF_TX_EN_FRAC

(9) FRAC_CONF_TX_EN_FRAC

0x0

Fractional data-rates in Tx mode (banked)

(8) FRAC_CONF_RX_EN_FRAC

(8) FRAC_CONF_RX_EN_FRAC

0x0

Fractional data-rates in Rx mode (banked)

(7:4) CONV_CODES_POLY_CC_POLY_1

(7:4) CONV_CODES_POLY_CC_POLY_1

0xD

Second convolutional code (banked)

(3:0) CONV_CODES_POLY_CC_POLY_0

(3:0) CONV_CODES_POLY_CC_POLY_0

0xF

First convolutional code (banked)

0x40040844

RF0_REG11

(31) FILTER_GAIN_LIN_FILTER

(31) FILTER_GAIN_LIN_FILTER

0x0

Enable the linear filtering (banked)

(30) FILTER_GAIN_LOW_LIN_GAIN

(30) FILTER_GAIN_LOW_LIN_GAIN

0x0

Reduce the total gain by two if the linear gain is set (banked)

(29:27) FILTER_GAIN_GAIN_M

(29:27) FILTER_GAIN_GAIN_M

0x0

Mantissa of the final stage gain of the matched filter (banked)

(26:24) FILTER_GAIN_GAIN_E

(26:24) FILTER_GAIN_GAIN_E

0x0

Exponent of the final stage gain of the matched filter (banked)

(23:20) TX_MULT_TX_MULT_EXP

(23:20) TX_MULT_TX_MULT_EXP

0x2

Exponent of the Tx multiplier (banked)

(19:16) TX_MULT_TX_MULT_MAN

(19:16) TX_MULT_TX_MULT_MAN

0x9

Mantissa of the Tx multiplier (banked)

(15:12) TX_FRAC_CONF_TX_FRAC_DEN

(15:12) TX_FRAC_CONF_TX_FRAC_DEN

0x0

Denominator of the fractional data-rate in Tx mode (banked)

(11:8) TX_FRAC_CONF_TX_FRAC_NUM

(11:8) TX_FRAC_CONF_TX_FRAC_NUM

0x0

Numerator of the fractional data-rate in Tx mode (banked)

(7:4) RX_FRAC_CONF_RX_FRAC_DEN

(7:4) RX_FRAC_CONF_RX_FRAC_DEN

0x0

Denominator of the fractional data-rate in Rx mode (banked)

(3:0) RX_FRAC_CONF_RX_FRAC_NUM

(3:0) RX_FRAC_CONF_RX_FRAC_NUM

0x0

Numerator of the fractional data-rate in Rx mode (banked)

0x40040848

RF0_TX_PULSE_SHAPE_1

(31:24) TX_PULSE_SHAPE_1_TX_COEF4

(31:24) TX_PULSE_SHAPE_1_TX_COEF4

0x0

Tx pulse shape coefficient 4 (banked)

(23:16) TX_PULSE_SHAPE_1_TX_COEF3

(23:16) TX_PULSE_SHAPE_1_TX_COEF3

0x0

Tx pulse shape coefficient 3 (banked)

(15:8) TX_PULSE_SHAPE_1_TX_COEF2

(15:8) TX_PULSE_SHAPE_1_TX_COEF2

0x0

Tx pulse shape coefficient 2 (banked)

(7:0) TX_PULSE_SHAPE_1_TX_COEF1

(7:0) TX_PULSE_SHAPE_1_TX_COEF1

0x0

Tx pulse shape coefficient 1 (banked)

0x4004084C

RF0_TX_PULSE_SHAPE_2

(31:24) TX_PULSE_SHAPE_2_TX_COEF8

(31:24) TX_PULSE_SHAPE_2_TX_COEF8

0x2

Tx pulse shape coefficient 8 (banked)

(23:16) TX_PULSE_SHAPE_2_TX_COEF7

(23:16) TX_PULSE_SHAPE_2_TX_COEF7

0x1

Tx pulse shape coefficient 7 (banked)

(15:8) TX_PULSE_SHAPE_2_TX_COEF6

(15:8) TX_PULSE_SHAPE_2_TX_COEF6

0x0

Tx pulse shape coefficient 6 (banked)

(7:0) TX_PULSE_SHAPE_2_TX_COEF5

(7:0) TX_PULSE_SHAPE_2_TX_COEF5

0x0

Tx pulse shape coefficient 5 (banked)

0x40040850

RF0_TX_PULSE_SHAPE_3

(31:24) TX_PULSE_SHAPE_3_TX_COEF12

(31:24) TX_PULSE_SHAPE_3_TX_COEF12

0x36

Tx pulse shape coefficient 12 (banked)

(23:16) TX_PULSE_SHAPE_3_TX_COEF11

(23:16) TX_PULSE_SHAPE_3_TX_COEF11

0x20

Tx pulse shape coefficient 11 (banked)

(15:8) TX_PULSE_SHAPE_3_TX_COEF10

(15:8) TX_PULSE_SHAPE_3_TX_COEF10

0x10

Tx pulse shape coefficient 10 (banked)

(7:0) TX_PULSE_SHAPE_3_TX_COEF9

(7:0) TX_PULSE_SHAPE_3_TX_COEF9

0x7

Tx pulse shape coefficient 9 (banked)

0x40040854

RF0_TX_PULSE_SHAPE_4

(31:24) TX_PULSE_SHAPE_4_TX_COEF16

(31:24) TX_PULSE_SHAPE_4_TX_COEF16

0x7D

Tx pulse shape coefficient 16 (banked)

(23:16) TX_PULSE_SHAPE_4_TX_COEF15

(23:16) TX_PULSE_SHAPE_4_TX_COEF15

0x75

Tx pulse shape coefficient 15 (banked)

(15:8) TX_PULSE_SHAPE_4_TX_COEF14

(15:8) TX_PULSE_SHAPE_4_TX_COEF14

0x66

Tx pulse shape coefficient 14 (banked)

(7:0) TX_PULSE_SHAPE_4_TX_COEF13

(7:0) TX_PULSE_SHAPE_4_TX_COEF13

0x4F

Tx pulse shape coefficient 13 (banked)

0x40040858

RF0_FRONTEND

(25:16) RX_IF_DIG_IF_DIG

(25:16) RX_IF_DIG_IF_DIG

0x40

IF frequency (banked)

(14:11) FRONTEND_RESAMPLE_PH_GAIN

(14:11) FRONTEND_RESAMPLE_PH_GAIN

0x6

Gain of the phase resampling block (banked)

(10:8) FRONTEND_RESAMPLE_RSSI_G2

(10:8) FRONTEND_RESAMPLE_RSSI_G2

0x0

Gain of the decimator in the RSSI resampling block (banked)

(7:6) FRONTEND_RESAMPLE_RSSI_G1

(7:6) FRONTEND_RESAMPLE_RSSI_G1

0x0

Gain of the interpolator in the RSSI resampling block (banked)

(5) FRONTEND_EN_RESAMPLE_RSSI

(5) FRONTEND_EN_RESAMPLE_RSSI

0x0

RSSI resampling (banked)

(4) FRONTEND_EN_RESAMPLE_PHADC

(4) FRONTEND_EN_RESAMPLE_PHADC

0x1

Phase resampling (banked)

(3:0) FRONTEND_DIV_PHADC

(3:0) FRONTEND_DIV_PHADC

0x0

Unsigned value that specifies the divider to obtain the phase ADC clock and RSSI (banked)

0x4004085C

RF0_RX_PULSE_SHAPE

(31:28) RX_PULSE_SHAPE_RX_COEF8

(31:28) RX_PULSE_SHAPE_RX_COEF8

0xF

Rx pulse shape coefficient 8 (banked)

(27:24) RX_PULSE_SHAPE_RX_COEF7

(27:24) RX_PULSE_SHAPE_RX_COEF7

0xE

Rx pulse shape coefficient 7 (banked)

(23:20) RX_PULSE_SHAPE_RX_COEF6

(23:20) RX_PULSE_SHAPE_RX_COEF6

0xC

Rx pulse shape coefficient 6 (banked)

(19:16) RX_PULSE_SHAPE_RX_COEF5

(19:16) RX_PULSE_SHAPE_RX_COEF5

0xA

Rx pulse shape coefficient 5 (banked)

(15:12) RX_PULSE_SHAPE_RX_COEF4

(15:12) RX_PULSE_SHAPE_RX_COEF4

0x7

Rx pulse shape coefficient 4 (banked)

(11:8) RX_PULSE_SHAPE_RX_COEF3

(11:8) RX_PULSE_SHAPE_RX_COEF3

0x4

Rx pulse shape coefficient 3 (banked)

(7:4) RX_PULSE_SHAPE_RX_COEF2

(7:4) RX_PULSE_SHAPE_RX_COEF2

0x2

Rx pulse shape coefficient 2 (banked)

(3:0) RX_PULSE_SHAPE_RX_COEF1

(3:0) RX_PULSE_SHAPE_RX_COEF1

0x1

Rx pulse shape coefficient 1 (banked)

0x40040860

RF0_REG18

(28) DELAY_LINE_CONF_MULTI_SYNC

(28) DELAY_LINE_CONF_MULTI_SYNC

0x0

Detect multiple syncs (banked)

(27:25) DELAY_LINE_CONF_DL_ISI_THR

(27:25) DELAY_LINE_CONF_DL_ISI_THR

0x1

Threshold bias for ISI compensation in the delay line sync word comparator (banked)

(22) DELAY_LINE_CONF_EN_SYNC_OK_DELAY_LINE

(22) DELAY_LINE_CONF_EN_SYNC_OK_DELAY_LINE

0x1

Use pattern_ok signal in delay line to synchronize the deserializer (banked)

(21:20) DELAY_LINE_CONF_MAX_ERR_IN_DL_SYNC

(21:20) DELAY_LINE_CONF_MAX_ERR_IN_DL_SYNC

0x0

Set the maximum errors in the delay line sync detection (banked)

(19) DELAY_LINE_CONF_EN_NOT_CAUSAL

(19) DELAY_LINE_CONF_EN_NOT_CAUSAL

0x0

Non causal processing (banked)

(18:16) DELAY_LINE_CONF_NC_SEL_OUT

(18:16) DELAY_LINE_CONF_NC_SEL_OUT

0x0

Select the output position for the non causal processing (banked)

(15:8) FSK_FCR_AMP_1_FSK_FCR_AMP1

(15:8) FSK_FCR_AMP_1_FSK_FCR_AMP1

0x1B

FSK amplitude low (banked)

(6:4) CARRIER_RECOVERY_EXTRA_FREQ_LIMIT_MAN

(6:4) CARRIER_RECOVERY_EXTRA_FREQ_LIMIT_MAN

0x5

Mantissa of the carrier recovery frequency limit (banked)

(2:0) CARRIER_RECOVERY_EXTRA_FREQ_LIMIT_EXP

(2:0) CARRIER_RECOVERY_EXTRA_FREQ_LIMIT_EXP

0x0

Exponent of the carrier recovery frequency limit (banked)

0x40040864

RF0_REG19

(30) RSSI_BANK_EN_RSSI_DITHER

(30) RSSI_BANK_EN_RSSI_DITHER

0x0

Speed on the RSSI triangular dithering signal (banked)

(29) RSSI_BANK_FAST_RSSI

(29) RSSI_BANK_FAST_RSSI

0x0

RSSI filtering speed (banked)

(28) RSSI_BANK_EN_FAST_PRE_SYNC

(28) RSSI_BANK_EN_FAST_PRE_SYNC

0x1

Fast mode switching during the preamble reception (banked)

(27:24) RSSI_BANK_TAU_RSSI_FILTERING

(27:24) RSSI_BANK_TAU_RSSI_FILTERING

0x1

Time constant of the RSSI filtering block (banked)

(20) DECISION_USE_VIT_SOFT

(20) DECISION_USE_VIT_SOFT

0x0

Viterbi soft decoding (banked)

(19:18) DECISION_VITERBI_LEN

(19:18) DECISION_VITERBI_LEN

0x2

Set the Viterbi path length (banked)

(17) DECISION_VITERBI_POW_NLIN

(17) DECISION_VITERBI_POW_NLIN

0x1

Viterbi algorithm uses power instead of amplitude to evaluate the error on the path (banked)

(16) DECISION_EN_VITERBI_GFSK

(16) DECISION_EN_VITERBI_GFSK

0x1

Viterbi algorithm for the GFSK decoding (banked)

(15:8) FSK_FCR_AMP_3_FSK_FCR_AMP3

(15:8) FSK_FCR_AMP_3_FSK_FCR_AMP3

0x44

FSK amplitude high (banked)

(7:0) FSK_FCR_AMP_2_FSK_FCR_AMP2

(7:0) FSK_FCR_AMP_2_FSK_FCR_AMP2

0x30

FSK amplitude mid (banked)

0x40040868

RF0_REG1A

(28:24) PA_PWR_PA_PWR

(28:24) PA_PWR_PA_PWR

0xC

Signed value that sets the PA power

(22) RSSI_BANK_ALT_USE_RSSI_ALT

(22) RSSI_BANK_ALT_USE_RSSI_ALT

0x0

Use alternative RRSI configuration (banked)

(21) RSSI_BANK_ALT_FAST_RSSI_ALT

(21) RSSI_BANK_ALT_FAST_RSSI_ALT

0x0

RSSI filtering speed (banked)

(19:16) RSSI_BANK_ALT_TAU_RSSI_FILTERING_ALT

(19:16) RSSI_BANK_ALT_TAU_RSSI_FILTERING_ALT

0x3

Time constant of the RSSI filtering block (banked)

(15:0) CORRECT_CFREQ_IF_CORRECT_CFREQ_IF

(15:0) CORRECT_CFREQ_IF_CORRECT_CFREQ_IF

0x1555

Unsigned value that specifies the IF for the Rx mode (banked)

0x4004086C

RF0_REG1B

(31) PLL_BANK_EN_LOW_CHP_BIAS_TX

(31) PLL_BANK_EN_LOW_CHP_BIAS_TX

0x0

Set the en_low_chp_bias bit in Tx mode (banked)

(30) PLL_BANK_EN_LOW_CHP_BIAS_RX

(30) PLL_BANK_EN_LOW_CHP_BIAS_RX

0x1

Set the en_low_chp_bias bit in Rx mode (banked)

(29:28) PLL_BANK_PLL_FILTER_RES_TRIM_TX

(29:28) PLL_BANK_PLL_FILTER_RES_TRIM_TX

0x3

Modify the value of the loop filter resistor R2 when bit 5 is high in Tx mode (banked)

(27:24) PLL_BANK_IQ_PLL_0_TX

(27:24) PLL_BANK_IQ_PLL_0_TX

0x4

Charge pump bias for Tx case (banked)

(22) PLL_BANK_LOW_DR_TX

(22) PLL_BANK_LOW_DR_TX

0x0

Enable low data-rate mode in Tx mode (banked)

(21:20) PLL_BANK_PLL_FILTER_RES_TRIM_RX

(21:20) PLL_BANK_PLL_FILTER_RES_TRIM_RX

0x0

Modify the value of the loop filter resistor R2 when bit 5 is high in Rx mode (banked)

(19:16) PLL_BANK_IQ_PLL_0_RX

(19:16) PLL_BANK_IQ_PLL_0_RX

0xB

Charge pump bias for Rx (banked)

(15) ANACLK_USE_NEW_ANACK

(15) ANACLK_USE_NEW_ANACK

0x0

Use the new analog clock generator (banked)

(13:12) ANACLK_DIV_CK_RSSI

(13:12) ANACLK_DIV_CK_RSSI

0x0

Set the master clock divider for the RSSI clock (banked)

(11:10) ANACLK_DIV_CK_FILT

(11:10) ANACLK_DIV_CK_FILT

0x0

Set the master clock divider for the channel filter clock (banked)

(9:8) ANACLK_DIV_CK_PHADC

(9:8) ANACLK_DIV_CK_PHADC

0x0

Set the master clock divider for the phase ADC clock (banked)

(7:4) ANACLK_DIV_RSSI

(7:4) ANACLK_DIV_RSSI

0x1

Unsigned value that specifies the division factor for the clock controlling the RSSI (banked)

(3:0) ANACLK_DIV_FILT

(3:0) ANACLK_DIV_FILT

0x5

Unsigned value that specifies the division factor for the clock controlling the channel filter (banked)

0x40040870

RF0_RSSI_CTRL

(31:30) RSSI_CTRL_AGC_DECAY_TAU

(31:30) RSSI_CTRL_AGC_DECAY_TAU

0x3

Time constant of the decay speed

(29) RSSI_CTRL_AGC_USE_LNA

(29) RSSI_CTRL_AGC_USE_LNA

0x1

AGC algorithm uses LNA bias

(28) RSSI_CTRL_AGC_MODE

(28) RSSI_CTRL_AGC_MODE

0x1

AGC algorithm selection

(27:26) RSSI_CTRL_AGC_WAIT

(27:26) RSSI_CTRL_AGC_WAIT

0x3

Set the wait time of the AGC after switching between state

(25) RSSI_CTRL_PAYLOAD_BLOCKS_AGC

(25) RSSI_CTRL_PAYLOAD_BLOCKS_AGC

0x1

AGC payload blocking

(24) RSSI_CTRL_BYPASS_AGC

(24) RSSI_CTRL_BYPASS_AGC

0x0

AGC algorithm bypass

(20:16) PA_PWR_OFFSET_PA_PWR_OFFSET

(20:16) PA_PWR_OFFSET_PA_PWR_OFFSET

0x0

Signed value that sets the PA power (banked)

(12:8) FILTER_BIAS_IQ_FI_BW

(12:8) FILTER_BIAS_IQ_FI_BW

0x14

Bias for the bandwidth of the channel filter (banked)

(4:0) FILTER_BIAS_IQ_FI_FC

(4:0) FILTER_BIAS_IQ_FI_FC

0xB

Bias for the central frequency of the channel filter (banked)

0x40040874

RF0_REG1D

(31:28) AGC_PEAK_DET_PEAK_DET_TAU

(31:28) AGC_PEAK_DET_PEAK_DET_TAU

0x7

Time constant of the peak detector monostable circuit

(27:26) AGC_PEAK_DET_PEAK_DET_THR_LOW

(27:26) AGC_PEAK_DET_PEAK_DET_THR_LOW

0x0

Threshold for the low level of the peak detector

(25) AGC_PEAK_DET_PEAK_DET_THR_HIGH

(25) AGC_PEAK_DET_PEAK_DET_THR_HIGH

0x0

Threshold for the high level of the peak detector

(24) AGC_PEAK_DET_EN_AGC_PEAK

(24) AGC_PEAK_DET_EN_AGC_PEAK

0x1

Enable AGC peak detector

(23:16) AGC_THR_HIGH_AGC_THR_HIGH

(23:16) AGC_THR_HIGH_AGC_THR_HIGH

0x69

AGC threshold high level (banked)

(15:8) AGC_THR_LOW_AGC_THR_LOW

(15:8) AGC_THR_LOW_AGC_THR_LOW

0x40

AGC threshold low level (banked)

(7:4) ATT_CTRL_ATT_CTRL_MAX

(7:4) ATT_CTRL_ATT_CTRL_MAX

0xB

Maximum attenuation level in AGC algorithm

(3:0) ATT_CTRL_SET_RX_ATT_CTRL

(3:0) ATT_CTRL_SET_RX_ATT_CTRL

0x0

Attenuation level if the AGC is bypassed

0x40040878

RF0_AGC_LUT1

(31:22) AGC_LUT_1_AGC_LEVEL_2_LO

(31:22) AGC_LUT_1_AGC_LEVEL_2_LO

0x280

AGC values level 2 (LSB)

(21:11) AGC_LUT_1_AGC_LEVEL_1

(21:11) AGC_LUT_1_AGC_LEVEL_1

0x80

AGC values level 1

(10:0) AGC_LUT_1_AGC_LEVEL_0

(10:0) AGC_LUT_1_AGC_LEVEL_0

0x0

AGC values level 0

0x4004087C

RF0_AGC_LUT2

(31:23) AGC_LUT_2_AGC_LEVEL_5_LO

(31:23) AGC_LUT_2_AGC_LEVEL_5_LO

0x84

AGC values level 5 (LSB)

(22:12) AGC_LUT_2_AGC_LEVEL_4

(22:12) AGC_LUT_2_AGC_LEVEL_4

0x284

AGC values level 4

(11:1) AGC_LUT_2_AGC_LEVEL_3

(11:1) AGC_LUT_2_AGC_LEVEL_3

0x480

AGC values level 3

(0) AGC_LUT_2_AGC_LEVEL_2_HI

(0) AGC_LUT_2_AGC_LEVEL_2_HI

0x0

AGC values level 2 (MSB)

0x40040880

RF0_AGC_LUT3

(31:24) AGC_LUT_3_AGC_LEVEL_8_LO

(31:24) AGC_LUT_3_AGC_LEVEL_8_LO

0x9D

AGC values level 8 (LSB)

(23:13) AGC_LUT_3_AGC_LEVEL_7

(23:13) AGC_LUT_3_AGC_LEVEL_7

0x495

AGC values level 7

(12:2) AGC_LUT_3_AGC_LEVEL_6

(12:2) AGC_LUT_3_AGC_LEVEL_6

0x485

AGC values level 6

(1:0) AGC_LUT_3_AGC_LEVEL_5_HI

(1:0) AGC_LUT_3_AGC_LEVEL_5_HI

0x2

AGC values level 5 (MSB)

0x40040884

RF0_AGC_LUT4

(31:25) AGC_LUT_4_AGC_LEVEL_11_LO

(31:25) AGC_LUT_4_AGC_LEVEL_11_LO

0x7F

AGC values level 11 (LSB)

(24:14) AGC_LUT_4_AGC_LEVEL_10

(24:14) AGC_LUT_4_AGC_LEVEL_10

0x4FF

AGC values level 10

(13:3) AGC_LUT_4_AGC_LEVEL_9

(13:3) AGC_LUT_4_AGC_LEVEL_9

0x49F

AGC values level 9

(2:0) AGC_LUT_4_AGC_LEVEL_8_HI

(2:0) AGC_LUT_4_AGC_LEVEL_8_HI

0x4

AGC values level 8 (MSB)

0x40040888

RF0_AGC_LUT5

(26:25) IEEE802154_OPTS_CNT_LIM_802154

(26:25) IEEE802154_OPTS_CNT_LIM_802154

0x2

Set the number of samples to wait before increasing the threshold

(24:22) IEEE802154_OPTS_CNT_OK_INC_802154

(24:22) IEEE802154_OPTS_CNT_OK_INC_802154

0x4

Set the increment to the counter that indicates that the correlators peaks are coherent

(21) IEEE802154_OPTS_USE_OS_802154

(21) IEEE802154_OPTS_USE_OS_802154

0x1

Enable the new algorithm working in the oversampled domain for the demodulation of the IEEE 802.15.4 protocol

(20) IEEE802154_OPTS_EN_DW_TEST

(20) IEEE802154_OPTS_EN_DW_TEST

0x0

Tx data-whitening before the convolutional code block

(18:16) IEEE802154_OPTS_C2B_THR

(18:16) IEEE802154_OPTS_C2B_THR

0x4

Threshold of the chip2bit correlator of the IEEE 802.15.4 protocol

(13:12) DATA_STREAMS_BER_CLK_MODE

(13:12) DATA_STREAMS_BER_CLK_MODE

0x0

Set the clock output mode for BER mode or RW mode

(10) DATA_STREAMS_RX_DATA_NOT_SAMPLED

(10) DATA_STREAMS_RX_DATA_NOT_SAMPLED

0x0

Signal rx_data in test modes sampling

(9) DATA_STREAMS_PHASE_GREY

(9) DATA_STREAMS_PHASE_GREY

0x0

Phase signal encoding

(8) DATA_STREAMS_TX_IN_CLK_TOGGLE

(8) DATA_STREAMS_TX_IN_CLK_TOGGLE

0x0

Input clock

(3:0) AGC_LUT_5_AGC_LEVEL_11_HI

(3:0) AGC_LUT_5_AGC_LEVEL_11_HI

0xE

AGC values level 11 (MSB)

0x4004088C

RF0_AGC_ATT1

(31:30) AGC_ATT_1_AGC_ATT_AB_LO

(31:30) AGC_ATT_1_AGC_ATT_AB_LO

0x3

AGC attenuation step 10/11 (LSB)

(29:27) AGC_ATT_1_AGC_ATT_9A

(29:27) AGC_ATT_1_AGC_ATT_9A

0x5

AGC attenuation step 9/10

(26:24) AGC_ATT_1_AGC_ATT_89

(26:24) AGC_ATT_1_AGC_ATT_89

0x3

AGC attenuation step 8/9

(23:21) AGC_ATT_1_AGC_ATT_78

(23:21) AGC_ATT_1_AGC_ATT_78

0x4

AGC attenuation step 7/8

(20:18) AGC_ATT_1_AGC_ATT_67

(20:18) AGC_ATT_1_AGC_ATT_67

0x3

AGC attenuation step 6/7

(17:15) AGC_ATT_1_AGC_ATT_56

(17:15) AGC_ATT_1_AGC_ATT_56

0x2

AGC attenuation step 5/6

(14:12) AGC_ATT_1_AGC_ATT_45

(14:12) AGC_ATT_1_AGC_ATT_45

0x2

AGC attenuation step 4/5

(11:9) AGC_ATT_1_AGC_ATT_34

(11:9) AGC_ATT_1_AGC_ATT_34

0x2

AGC attenuation step 3/4

(8:6) AGC_ATT_1_AGC_ATT_23

(8:6) AGC_ATT_1_AGC_ATT_23

0x1

AGC attenuation step 2/3

(5:3) AGC_ATT_1_AGC_ATT_12

(5:3) AGC_ATT_1_AGC_ATT_12

0x1

AGC attenuation step 1/2

(2:0) AGC_ATT_1_AGC_ATT_01

(2:0) AGC_ATT_1_AGC_ATT_01

0x4

AGC attenuation step 0/1

0x40040890

RF0_AGC_ATT2

(31:28) TIMINGS_3_T_DLL

(31:28) TIMINGS_3_T_DLL

0x2

Time needed by the DLL blocks to switch on

(27:24) TIMINGS_3_T_PLL_TX

(27:24) TIMINGS_3_T_PLL_TX

0x2

Time needed by the PLL blocks in Tx mode to switch on

(23:20) TIMINGS_2_T_SUBBAND_TX

(23:20) TIMINGS_2_T_SUBBAND_TX

0xC

Time needed by the subband algorithm to calibrate in Tx mode

(19:16) TIMINGS_2_T_TX_RF

(19:16) TIMINGS_2_T_TX_RF

0x1

Time needed by the RF blocks to switch on in Tx mode

(14:12) TIMINGS_1_T_GRANULARITY_TX

(14:12) TIMINGS_1_T_GRANULARITY_TX

0x3

Define the granularity of the timer in Tx mode

(10:8) TIMINGS_1_T_GRANULARITY_RX

(10:8) TIMINGS_1_T_GRANULARITY_RX

0x5

Define the granularity of the timer in Rx mode

(1) AGC_ATT_2_AGC_ATT_1DB

(1) AGC_ATT_2_AGC_ATT_1DB

0x0

Attenuation steps

(0) AGC_ATT_2_AGC_ATT_AB_HI

(0) AGC_ATT_2_AGC_ATT_AB_HI

0x1

AGC attenuation step 10/11 (MSB)

0x40040894

RF0_REG25

(31) TIMEOUT_EN_RX_TIMEOUT

(31) TIMEOUT_EN_RX_TIMEOUT

0x0

Timeout of the Rx when the system is on FSM mode

(30:28) TIMEOUT_T_TIMEOUT_GR

(30:28) TIMEOUT_T_TIMEOUT_GR

0x0

Granularity of the timer in timeout Rx mode

(27:24) TIMEOUT_T_RX_TIMEOUT

(27:24) TIMEOUT_T_RX_TIMEOUT

0x0

Time that has to occur before the timeout

(21) TIMING_FAST_RX_EN_FAST_RX_TXFILT

(21) TIMING_FAST_RX_EN_FAST_RX_TXFILT

0x0

Filter Tx configuration for the fast Rx PLL

(20) TIMING_FAST_RX_EN_FAST_RX

(20) TIMING_FAST_RX_EN_FAST_RX

0x0

Fast Rx PLL

(19:16) TIMING_FAST_RX_T_RX_FAST_CHP

(19:16) TIMING_FAST_RX_T_RX_FAST_CHP

0x0

Time to switch off the fast CHP in Rx mode

(15:12) TIMINGS_5_T_RX_RF

(15:12) TIMINGS_5_T_RX_RF

0x0

Time needed by the RF blocks to switch on in Rx mode

(11:8) TIMINGS_5_T_RX_BB

(11:8) TIMINGS_5_T_RX_BB

0x1

Time needed by the BB blocks to switch on in Rx mode

(7:4) TIMINGS_4_T_SUBBAND_RX

(7:4) TIMINGS_4_T_SUBBAND_RX

0x5

Time needed by the subband algorithm to calibrate in Rx mode

(3:0) TIMINGS_4_T_PLL_RX

(3:0) TIMINGS_4_T_PLL_RX

0x1

Time needed by the PLL blocks to switch on in Rx mode

0x40040898

RF0_BIAS_0_2

(31:28) BIAS_2_IQ_RXTX_6

(31:28) BIAS_2_IQ_RXTX_6

0x3

VCOM_MX bias

(27:24) BIAS_2_IQ_RXTX_5

(27:24) BIAS_2_IQ_RXTX_5

0x8

VCOM_LO bias

(23:20) BIAS_1_IQ_RXTX_3

(23:20) BIAS_1_IQ_RXTX_3

0x6

PrePA Casc bias

(19:16) BIAS_1_IQ_RXTX_2

(19:16) BIAS_1_IQ_RXTX_2

0x6

PrePA In bias

(15:12) BIAS_0_IQ_RXTX_1

(15:12) BIAS_0_IQ_RXTX_1

0x7

PA backoff bias

(11:8) BIAS_0_IQ_RXTX_0

(11:8) BIAS_0_IQ_RXTX_0

0x3

PA bias

(7) INTERFACE_CONF_EN_SYNC_IFACE

(7) INTERFACE_CONF_EN_SYNC_IFACE

0x0

Interfaces resynchronization

(6:4) INTERFACE_CONF_APB_WAIT_STATE

(6:4) INTERFACE_CONF_APB_WAIT_STATE

0x0

Select the number of wait states during the APB transaction

(1:0) INTERFACE_CONF_SPI_SELECT

(1:0) INTERFACE_CONF_SPI_SELECT

0x0

Select the SPI mode

0x4004089C

RF0_BIAS_3_6

(31:28) BIAS_6_IQ_BB_0

(31:28) BIAS_6_IQ_BB_0

0x7

ACD_O bias

(27:24) BIAS_6_IQ_PLL_3

(27:24) BIAS_6_IQ_PLL_3

0x7

DLL bias

(23:20) BIAS_5_IQ_PLL_4_RX

(23:20) BIAS_5_IQ_PLL_4_RX

0x8

VCO bias for Rx mode

(19:16) BIAS_5_IQ_PLL_4_TX

(19:16) BIAS_5_IQ_PLL_4_TX

0xA

VCO bias for Tx mode

(15:12) BIAS_4_IQ_PLL_2

(15:12) BIAS_4_IQ_PLL_2

0x7

Sub-band comparator bias

(11:8) BIAS_4_IQ_PLL_1

(11:8) BIAS_4_IQ_PLL_1

0x4

Dynamic divider bias

(7:4) BIAS_3_IQ_RXTX_8

(7:4) BIAS_3_IQ_RXTX_8

0x7

IFA ctrl_c bias

(3:0) BIAS_3_IQ_RXTX_7

(3:0) BIAS_3_IQ_RXTX_7

0x7

IFA ctrl_r bias

0x400408A0

RF0_BIAS_7_9

(31:28) BIAS_9_IQ_BB_6

(31:28) BIAS_9_IQ_BB_6

0x9

Peak detector threshold bias 0

(27:24) BIAS_9_IQ_BB_5

(27:24) BIAS_9_IQ_BB_5

0x5

Peak detector bias

(23:20) SWCAP_FSM_SB_CAP_RX

(23:20) SWCAP_FSM_SB_CAP_RX

0x0

VCO subband selection (FSM in Rx mode)

(19:16) SWCAP_FSM_SB_CAP_TX

(19:16) SWCAP_FSM_SB_CAP_TX

0x0

VCO subband selection (FSM in Tx mode)

(15:12) BIAS_8_IQ_BB_4

(15:12) BIAS_8_IQ_BB_4

0x9

RSSI_D bias

(11:8) BIAS_8_IQ_BB_3

(11:8) BIAS_8_IQ_BB_3

0xF

RSSI_G bias

(7:4) BIAS_7_IQ_BB_2

(7:4) BIAS_7_IQ_BB_2

0x6

ACD_L bias

(3:0) BIAS_7_IQ_BB_1

(3:0) BIAS_7_IQ_BB_1

0x6

ACD_C bias

0x400408A4

RF0_BIAS_10_12

(30) SD_MASH_MASH_DITHER_TYPE

(30) SD_MASH_MASH_DITHER_TYPE

0x0

Enable the new dithering scheme

(29) SD_MASH_MASH_ENABLE

(29) SD_MASH_MASH_ENABLE

0x0

Enable the sigma delta mash

(28) SD_MASH_MASH_DITHER

(28) SD_MASH_MASH_DITHER

0x1

Enable dithering on the sigma delta mash

(27:25) SD_MASH_MASH_ORDER

(27:25) SD_MASH_MASH_ORDER

0x3

Order of the sigma delta mash

(24) SD_MASH_MASH_RSTB

(24) SD_MASH_MASH_RSTB

0x1

Reset of the sigma delta mash (active low)

(23:20) BIAS_12_LNA_AGC_BIAS_3

(23:20) BIAS_12_LNA_AGC_BIAS_3

0x6

LNA bias for AGC level 3

(19:16) BIAS_12_LNA_AGC_BIAS_2

(19:16) BIAS_12_LNA_AGC_BIAS_2

0x7

LNA bias for AGC level 2

(15:12) BIAS_11_LNA_AGC_BIAS_1

(15:12) BIAS_11_LNA_AGC_BIAS_1

0x8

LNA bias for AGC level 1

(11:8) BIAS_11_LNA_AGC_BIAS_0

(11:8) BIAS_11_LNA_AGC_BIAS_0

0x9

LNA bias for AGC level 0

(7:4) BIAS_10_IQ_BB_8

(7:4) BIAS_10_IQ_BB_8

0x0

Peak detector threshold bias 1

(3:0) BIAS_10_IQ_BB_7

(3:0) BIAS_10_IQ_BB_7

0x6

Peak detector threshold bias 2

0x400408A8

RF0_REG2A

(27:24) SD_MASH_MASK_MASH_MASK

(27:24) SD_MASH_MASK_MASH_MASK

0x0

Mask the n LSB of the fractional part of the MASH (debug only)

(19) BIAS_EN_2_EN_PTAT

(19) BIAS_EN_2_EN_PTAT

0x1

Enable PTAT

(18:16) BIAS_EN_2_EN_BIAS_BB_HI

(18:16) BIAS_EN_2_EN_BIAS_BB_HI

0x0

Bias enable for BB (same order as biases)

(15:12) BIAS_EN_1_EN_BIAS_BB_LO

(15:12) BIAS_EN_1_EN_BIAS_BB_LO

0x0

Bias enable for BB (same order as biases)

(11:7) BIAS_EN_1_EN_BIAS_PLL

(11:7) BIAS_EN_1_EN_BIAS_PLL

0x0

Bias enable for PLL (same order as biases)

(6:0) BIAS_EN_1_EN_BIAS_RXTX

(6:0) BIAS_EN_1_EN_BIAS_RXTX

0x0

Bias enable for RxTx (same order as biases)

0x400408AC

RF0_PLL_CTRL

(26) PLL_CTRL_DISABLE_CHP_SBS

(26) PLL_CTRL_DISABLE_CHP_SBS

0x0

Charge-pump disabling during sub-band selection (FLL and frequency ratios)

(25) PLL_CTRL_PLL_RX_48MEG

(25) PLL_CTRL_PLL_RX_48MEG

0x1

PLL frequency

(24) PLL_CTRL_SWCAP_TX_SAME_RX

(24) PLL_CTRL_SWCAP_TX_SAME_RX

0x0

Registers for Rx and Tx modes swcap in case of swcap_fsm=1

(23) PLL_CTRL_SWCAP_FSM

(23) PLL_CTRL_SWCAP_FSM

0x1

Selection of the swcap_fsm register

(22) PLL_CTRL_DLL_RSTB

(22) PLL_CTRL_DLL_RSTB

0x1

Reset signal of the DLL (active low)

(21:18) PLL_CTRL_VCO_SUBBAND_TRIM

(21:18) PLL_CTRL_VCO_SUBBAND_TRIM

0x0

VCO sub-band selection bits

(17) PLL_CTRL_SUB_SEL_OFFS_EN

(17) PLL_CTRL_SUB_SEL_OFFS_EN

0x0

Add offset to sub-band selection comparator

(16) PLL_CTRL_DIV2_CLKVCO_TEST_EN

(16) PLL_CTRL_DIV2_CLKVCO_TEST_EN

0x0

VCO signal divided by the programmable divider

(15) PLL_CTRL_VCODIV_CLK_TEST_EN

(15) PLL_CTRL_VCODIV_CLK_TEST_EN

0x0

Output on GPIO the VCO signal divided by the programmable divider

(13) PLL_CTRL_CHP_DEAD_ZONE_EN

(13) PLL_CTRL_CHP_DEAD_ZONE_EN

0x0

Charge-pump dead zone

(12:11) PLL_CTRL_CHP_CURR_OFF_TRIM_TX

(12:11) PLL_CTRL_CHP_CURR_OFF_TRIM_TX

0x3

Charge-pump offset current values selection bits in Tx mode

(10:9) PLL_CTRL_CHP_CURR_OFF_TRIM_RX

(10:9) PLL_CTRL_CHP_CURR_OFF_TRIM_RX

0x3

Charge-pump offset current values selection bits in Rx mode

(8) PLL_CTRL_HIGH_BW_FILTER_EN_TX

(8) PLL_CTRL_HIGH_BW_FILTER_EN_TX

0x1

PLL filter high bandwidth needed in Tx mode

(7) PLL_CTRL_HIGH_BW_FILTER_EN_RX

(7) PLL_CTRL_HIGH_BW_FILTER_EN_RX

0x0

PLL filter high bandwidth needed in Rx mode

(6) PLL_CTRL_FAST_CHP_EN_TX

(6) PLL_CTRL_FAST_CHP_EN_TX

0x1

High current output of the charge-pump for PLL Tx high bandwidth mode

(5) PLL_CTRL_FAST_CHP_EN_RX

(5) PLL_CTRL_FAST_CHP_EN_RX

0x0

High current output of the charge-pump for PLL Rx high bandwidth mode

(4:3) PLL_CTRL_CHP_MODE_TRIM

(4:3) PLL_CTRL_CHP_MODE_TRIM

0x0

Select the frequency inside sub-band selection

(2) PLL_CTRL_CHP_CMC_EN

(2) PLL_CTRL_CHP_CMC_EN

0x1

Common mode control block of the charge-pump

(1) PLL_CTRL_CHP_CURR_OFF_EN_TX

(1) PLL_CTRL_CHP_CURR_OFF_EN_TX

0x1

Charge-pump offset current in Tx mode

(0) PLL_CTRL_CHP_CURR_OFF_EN_RX

(0) PLL_CTRL_CHP_CURR_OFF_EN_RX

0x0

Charge-pump offset current in Rx mode

0x400408B0

RF0_DLL_CTRL

(31:29) RSSI_TUN_1_RSSI_TUN_GAIN

(31:29) RSSI_TUN_1_RSSI_TUN_GAIN

0x1

RSSI tuning for gain

(28:24) RSSI_TUN_1_RSSI_ODD_OFFSET

(28:24) RSSI_TUN_1_RSSI_ODD_OFFSET

0x4

RSSI tuning for odd stages (offset to the even triangular wave)

(23:20) RSSI_TUN_1_RSSI_EVEN_MAX

(23:20) RSSI_TUN_1_RSSI_EVEN_MAX

0x1

RSSI tuning for even stages (maximum value of the triangular wave)

(19:16) RSSI_TUN_1_RSSI_EVEN_MIN

(19:16) RSSI_TUN_1_RSSI_EVEN_MIN

0x1

RSSI tuning for even stages (minimum value of the triangular wave)

(12) DLL_CTRL_CK_LAST_SEL_DELAY

(12) DLL_CTRL_CK_LAST_SEL_DELAY

0x0

Last SEL delay

(11) DLL_CTRL_CK_FIRST_SEL_DELAY

(11) DLL_CTRL_CK_FIRST_SEL_DELAY

0x0

First SEL delay

(10) DLL_CTRL_CK_EXT_SEL

(10) DLL_CTRL_CK_EXT_SEL

0x0

Input clock selection

(9) DLL_CTRL_CK_DIG_EN

(9) DLL_CTRL_CK_DIG_EN

0x0

Alternate ck_dig pin to output the PLL reference clock signal

(8) DLL_CTRL_CK_TEST_EN

(8) DLL_CTRL_CK_TEST_EN

0x0

Output on GPIO the PLL reference clock signal via ck_test pin

(7) DLL_CTRL_TOO_FAST_ENB

(7) DLL_CTRL_TOO_FAST_ENB

0x0

Lock range phase detector

(6) DLL_CTRL_LOCKED_DET_EN

(6) DLL_CTRL_LOCKED_DET_EN

0x1

Reference frequency multiplier locked detector

(5) DLL_CTRL_LOCKED_AUTO_CHECK_EN

(5) DLL_CTRL_LOCKED_AUTO_CHECK_EN

0x1

Frequency multiplier is out of lock (usually because some input clocks from ck_xtal or ck_ext are missing)

(4) DLL_CTRL_FAST_ENB

(4) DLL_CTRL_FAST_ENB

0x0

Disable fast mode locking of the reference frequency multiplier

(3:2) DLL_CTRL_CK_SEL_TX

(3:2) DLL_CTRL_CK_SEL_TX

0x1

Selection of the clock used as frequency reference of the PLL in Tx mode (also to ck_test and ck_dig outputs)

(1:0) DLL_CTRL_CK_SEL_RX

(1:0) DLL_CTRL_CK_SEL_RX

0x0

Selection of the clock used as frequency reference of the PLL in Rx mode (also to ck_test and ck_dig outputs)

0x400408B4

RF0_REG2D

(29:28) PA_CONF_SW_CN

(29:28) PA_CONF_SW_CN

0x0

Harmonic 2 notch tuning

(27) PA_CONF_TX_SWITCHPA

(27) PA_CONF_TX_SWITCHPA

0x0

Switch PA

(26) PA_CONF_TX_0DBM

(26) PA_CONF_TX_0DBM

0x1

Select between PPA and PA

(25) PA_CONF_LIN_RAMP

(25) PA_CONF_LIN_RAMP

0x0

PA ramp-up linearization

(24) PA_CONF_MIN_PA_PWR

(24) PA_CONF_MIN_PA_PWR

0x1

Set the minimum power during the PA ramp-up

(23) CTRL_RX_SWITCH_LP

(23) CTRL_RX_SWITCH_LP

0x0

Switch the low-pass filter in the Rx chain

(22) CTRL_RX_USE_PEAK_DETECTOR

(22) CTRL_RX_USE_PEAK_DETECTOR

0x1

Peak detector powering

(21) CTRL_RX_START_MIX_ON_CAL

(21) CTRL_RX_START_MIX_ON_CAL

0x0

Mixer enabling

(20:16) CTRL_RX_CTRL_RX

(20:16) CTRL_RX_CTRL_RX

0xF

Rx control

(15) CTRL_ADC_PHADC_THERM_OUT_EN

(15) CTRL_ADC_PHADC_THERM_OUT_EN

0x1

Enable the buffers of phase ADC thermometric code (banked)

(14:13) CTRL_ADC_PHADC_DELLATCH

(14:13) CTRL_ADC_PHADC_DELLATCH

0x1

Phase ADC delay latch trimming (banked)

(12:8) CTRL_ADC_CTRL_ADC

(12:8) CTRL_ADC_CTRL_ADC

0x5

Phase ADC control (banked)

(6:5) RSSI_TUN_2_RSSI_TRI_CK_DIV

(6:5) RSSI_TUN_2_RSSI_TRI_CK_DIV

0x0

Speed on the RSSI triangular dithering signal (cf reg RSSI_TUN)

(4) RSSI_TUN_2_RSSI_ONE_CK_RSSI_PHADC

(4) RSSI_TUN_2_RSSI_ONE_CK_RSSI_PHADC

0x0

RSSI and phase ADC clocks sharing

(3) RSSI_TUN_2_RSSI_FULL

(3) RSSI_TUN_2_RSSI_FULL

0x1

RSSI full scale

(2) RSSI_TUN_2_RSSI_1DB

(2) RSSI_TUN_2_RSSI_1DB

0x0

LSB resolution

(1:0) RSSI_TUN_2_RSSI_PRE_ATT

(1:0) RSSI_TUN_2_RSSI_PRE_ATT

0x3

Pre attenuation of the RSSI signal

0x400408B8

RF0_REG2E

(31:24) XTAL_TRIM_XTAL_TRIM_INIT

(31:24) XTAL_TRIM_XTAL_TRIM_INIT

0x60

Initial trimming of the XTAL

(23:16) XTAL_TRIM_XTAL_TRIM

(23:16) XTAL_TRIM_XTAL_TRIM

0x60

Trimming of the XTAL

(12) ENABLES_SEPARATE_PPA_CASC

(12) ENABLES_SEPARATE_PPA_CASC

0x0

PA cascode bit

(11:6) ENABLES_EN_RXTX

(11:6) ENABLES_EN_RXTX

0x0

Enable signals

(5:0) ENABLES_EN_BB

(5:0) ENABLES_EN_BB

0x0

Enable signals for the BB

0x400408BC

RF0_XTAL_CTRL

(31:28) XTAL_CTRL_XO_THR_HIGH

(31:28) XTAL_CTRL_XO_THR_HIGH

0xC

High threshold for XTAL trimming

(27:24) XTAL_CTRL_XO_THR_LOW

(27:24) XTAL_CTRL_XO_THR_LOW

0x3

Low threshold for XTAL trimming

(23:22) XTAL_CTRL_XO_A_S_CURR_SEL_HIGH

(23:22) XTAL_CTRL_XO_A_S_CURR_SEL_HIGH

0x2

Value of after_startup_curr_sel when level is higher than xo_thr_high

(21:20) XTAL_CTRL_XO_A_S_CURR_SEL_LOW

(21:20) XTAL_CTRL_XO_A_S_CURR_SEL_LOW

0x0

Value of after_startup_curr_sel when level is lower than xo_thr_low

(19) XTAL_CTRL_LOW_CLK_READY_TH_EN

(19) XTAL_CTRL_LOW_CLK_READY_TH_EN

0x0

clk_ready threshold

(18) XTAL_CTRL_XTAL_CTRL_BYPASS

(18) XTAL_CTRL_XTAL_CTRL_BYPASS

0x0

Bypass the XTAL control algorithm

(17) XTAL_CTRL_DIG_CLK_IN_SEL

(17) XTAL_CTRL_DIG_CLK_IN_SEL

0x0

Clock selection for the digital block

(16) XTAL_CTRL_XO_EN_B_REG

(16) XTAL_CTRL_XO_EN_B_REG

0x1

XTAL oscillator enable

(15:14) XTAL_CTRL_XTAL_CKDIV

(15:14) XTAL_CTRL_XTAL_CKDIV

0x0

XTAL trimming speed

(13) XTAL_CTRL_CLK_OUT_EN_B

(13) XTAL_CTRL_CLK_OUT_EN_B

0x0

Output clock to go to main IP

(12) XTAL_CTRL_REG_VALUE_SEL

(12) XTAL_CTRL_REG_VALUE_SEL

0x0

Control bits of xtal_reg

(11:10) XTAL_CTRL_AFTERSTARTUP_CURR_SEL

(11:10) XTAL_CTRL_AFTERSTARTUP_CURR_SEL

0x1

Selection of the current before amplitude stabilization but after starting-up in active transistors of the core oscillator

(9:8) XTAL_CTRL_STARTUP_CURR_SEL

(9:8) XTAL_CTRL_STARTUP_CURR_SEL

0x1

Selection of the starting-up current in active transistors of the core oscillator

(7) XTAL_CTRL_INV_CLK_DIG

(7) XTAL_CTRL_INV_CLK_DIG

0x0

Invert clock on clk_dig output

(6) XTAL_CTRL_INV_CLK_PLL

(6) XTAL_CTRL_INV_CLK_PLL

0x0

Invert clock on clk_pll output

(5) XTAL_CTRL_FORCE_CLK_READY

(5) XTAL_CTRL_FORCE_CLK_READY

0x0

Force output clocks on clk_pll, clk_dig and clk_out

(4) XTAL_CTRL_CLK_DIG_EN_B

(4) XTAL_CTRL_CLK_DIG_EN_B

0x0

Disable the output clock to go to digital (clk_dig output stay low)

(3) XTAL_CTRL_BUFF_EN_B

(3) XTAL_CTRL_BUFF_EN_B

0x0

XTAL buffer disabling

(2) XTAL_CTRL_HP_MODE

(2) XTAL_CTRL_HP_MODE

0x0

Bias current increase in the clock buffer

(1) XTAL_CTRL_LP_MODE

(1) XTAL_CTRL_LP_MODE

0x0

Bias current decrease in the clock buffer

(0) XTAL_CTRL_EXT_CLK_MODE

(0) XTAL_CTRL_EXT_CLK_MODE

0x0

Use XTAL pads as external clock input

0x400408C0

RF0_SUBBAND

(31:24) SUBBAND_OFFSET_SB_OFFSET_RX

(31:24) SUBBAND_OFFSET_SB_OFFSET_RX

0xF1

Offset to add in frequency count in order to compensate the offset of the varicap

(23:16) SUBBAND_OFFSET_SB_OFFSET

(23:16) SUBBAND_OFFSET_SB_OFFSET

0xD0

Offset to add in frequency count in order to compensate the offset of the varicap

(15:12) SWCAP_LIM_SB_MAX_VAL

(15:12) SWCAP_LIM_SB_MAX_VAL

0xF

Maximum subband value in linear search subband (freq and comp)

(11:8) SWCAP_LIM_SB_MIN_VAL

(11:8) SWCAP_LIM_SB_MIN_VAL

0x0

Minimum subband value in linear search subband (freq and comp)

(7) SUBBAND_CONF_SB_FLL_MODE

(7) SUBBAND_CONF_SB_FLL_MODE

0x1

FLL mode for the subband selection

(6) SUBBAND_CONF_SB_INV_BAND

(6) SUBBAND_CONF_SB_INV_BAND

0x0

Invert the meaning of sb_high and sb_low

(5:4) SUBBAND_CONF_SB_FREQ_CNT

(5:4) SUBBAND_CONF_SB_FREQ_CNT

0x0

The length to count in frequency mode

(3:2) SUBBAND_CONF_SB_WAIT_T

(3:2) SUBBAND_CONF_SB_WAIT_T

0x0

Time to wait to the PLL to settle

(1:0) SUBBAND_CONF_SB_MODE

(1:0) SUBBAND_CONF_SB_MODE

0x0

Sub-band algorithm mode

0x400408C4

RF0_REG31

(31:30) RSSI_DETECT_RSSI_DET_CR_LEN

(31:30) RSSI_DETECT_RSSI_DET_CR_LEN

0x0

Number of samples to estimate the carrier offset (banked)

(29:28) RSSI_DETECT_RSSI_DET_WAIT

(29:28) RSSI_DETECT_RSSI_DET_WAIT

0x0

Symbols to wait after the RSSI detection (banked)

(27:26) RSSI_DETECT_RSSI_DET_DIFF_LL

(27:26) RSSI_DETECT_RSSI_DET_DIFF_LL

0x0

Set the distance between the actual value and the subtracted one (banked)

(25) RSSI_DETECT_EN_ABS_RSSI_DETECT

(25) RSSI_DETECT_EN_ABS_RSSI_DETECT

0x0

Absolute RSSI detection (banked)

(24) RSSI_DETECT_EN_DIFF_RSSI_DETECT

(24) RSSI_DETECT_EN_DIFF_RSSI_DETECT

0x0

Differential RSSI detection (banked)

(23) SUBBAND_CORR_SUBBAND_CORR_EN

(23) SUBBAND_CORR_SUBBAND_CORR_EN

0x0

Subband correction

(22:20) SUBBAND_CORR_SUBBAND_CORR_RX

(22:20) SUBBAND_CORR_SUBBAND_CORR_RX

0x0

Subband correction in Rx

(18:16) SUBBAND_CORR_SUBBAND_CORR_TX

(18:16) SUBBAND_CORR_SUBBAND_CORR_TX

0x0

Subband correction in Tx

(11) TXRX_CONF_INV_CLK_PLL_TX

(11) TXRX_CONF_INV_CLK_PLL_TX

0x0

Invert PLL clock when the radio is in Tx mode

(10) TXRX_CONF_INV_CLK_DIG_TX

(10) TXRX_CONF_INV_CLK_DIG_TX

0x0

Invert digital clock when the radio is in Tx mode

(9:8) TXRX_CONF_SB_WAIT_T_TX

(9:8) TXRX_CONF_SB_WAIT_T_TX

0x0

Xor value to apply to sb_wait_t (register SUBBAND_CONF) when the radio is in Tx mode

(7) PA_RAMPUP_FULL_PA_RAMPUP

(7) PA_RAMPUP_FULL_PA_RAMPUP

0x1

PA rampup configuration

(6:4) PA_RAMPUP_DEL_PA_RAMPUP

(6:4) PA_RAMPUP_DEL_PA_RAMPUP

0x4

Time to wait to start the ramp-up after the PA enable is detected

(3:2) PA_RAMPUP_TAU_PA_RAMPUP

(3:2) PA_RAMPUP_TAU_PA_RAMPUP

0x0

Time constant of the ramp-up/ramp-down

(1) PA_RAMPUP_EN_PA_RAMPDOWN

(1) PA_RAMPUP_EN_PA_RAMPDOWN

0x1

PA ramp-down

(0) PA_RAMPUP_EN_PA_RAMPUP

(0) PA_RAMPUP_EN_PA_RAMPUP

0x1

PA ramp-up linearization

0x400408C8

RF0_DEMOD_CTRL

(31) SYNC_WORD_CORR_EN_SYNC_WORD_CORR

(31) SYNC_WORD_CORR_EN_SYNC_WORD_CORR

0x1

Sync word bias correction with RSSI detection (banked)

(29:24) SYNC_WORD_CORR_SYNC_WORD_BIAS

(29:24) SYNC_WORD_CORR_SYNC_WORD_BIAS

0x8

Set the sync word bias (banked)

(23:16) RSSI_DETECT_ABS_THR_RSSI_DET_ABS_THR

(23:16) RSSI_DETECT_ABS_THR_RSSI_DET_ABS_THR

0x0

Threshold used for absolute RSSI detection

(15:8) RSSI_DETECT_DIFF_THR_RSSI_DET_DIFF_THR

(15:8) RSSI_DETECT_DIFF_THR_RSSI_DET_DIFF_THR

0x0

Threshold used for differential RSSI detection

(7) DEMOD_CTRL_DL_SYNC_NO_DATA

(7) DEMOD_CTRL_DL_SYNC_NO_DATA

0x1

No data going through the demodulator, until the delay line detects the sync word (banked)

(6) DEMOD_CTRL_EN_DELLINE_SYNC_DET

(6) DEMOD_CTRL_EN_DELLINE_SYNC_DET

0x1

Sync word detection in the delay line (banked)

(5) DEMOD_CTRL_RSSI_DET_FILT

(5) DEMOD_CTRL_RSSI_DET_FILT

0x0

Additional filtering on the RSSI value (banked)

(4) DEMOD_CTRL_EN_FAST_CLK_RECOV

(4) DEMOD_CTRL_EN_FAST_CLK_RECOV

0x0

Clock recovery during the resto of the preamble (banked)

(3) DEMOD_CTRL_EN_MIN_MAX_MF

(3) DEMOD_CTRL_EN_MIN_MAX_MF

0x0

Min max algo after the matched filter (banked)

(2) DEMOD_CTRL_EN_PRE_SYNC

(2) DEMOD_CTRL_EN_PRE_SYNC

0x0

Sync detection on the non-delayed path (banked)

(1) DEMOD_CTRL_BLOCK_RSSI_DET

(1) DEMOD_CTRL_BLOCK_RSSI_DET

0x0

RSSI detection during the slow-down period (banked)

(0) DEMOD_CTRL_EARLY_FINE_RECOV

(0) DEMOD_CTRL_EARLY_FINE_RECOV

0x0

Early fine recovery after the packet detection or pre-sync (banked)

0x400408CC

RF0_REG33

(26:24) CK_DIV_1_6_CK_DIV_1_6

(26:24) CK_DIV_1_6_CK_DIV_1_6

0x0

Clock division factor for ck_div_1_6

(23:16) SPARES_SPARES

(23:16) SPARES_SPARES

0x0

Spare bits

(14) PADS_PE_DS_GPIO_DS

(14) PADS_PE_DS_GPIO_DS

0x0

Increased drive strength of the digital pads

(13) PADS_PE_DS_GPIO_PE

(13) PADS_PE_DS_GPIO_PE

0x0

Pull-up of the GPIO pads

(12) PADS_PE_DS_NRESET_PE

(12) PADS_PE_DS_NRESET_PE

0x0

Pull-up of the NRESET pads

(11) PADS_PE_DS_SPI_MISO_PE

(11) PADS_PE_DS_SPI_MISO_PE

0x0

Pull-up of the SPI MISO pads

(10) PADS_PE_DS_SPI_MOSI_PE

(10) PADS_PE_DS_SPI_MOSI_PE

0x0

Pull-up of the SPI MOSI pads

(9) PADS_PE_DS_SPI_SCLK_PE

(9) PADS_PE_DS_SPI_SCLK_PE

0x0

Pull-up of the SPI CLK pads

(8) PADS_PE_DS_SPI_CS_N_PE

(8) PADS_PE_DS_SPI_CS_N_PE

0x0

Pull-up of the SPI CSN pads

(7:6) SUBBAND_FLL_SB_FLL_DITHER

(7:6) SUBBAND_FLL_SB_FLL_DITHER

0x0

Select the dithering

(5:4) SUBBAND_FLL_SB_FLL_CIC_TAU

(5:4) SUBBAND_FLL_SB_FLL_CIC_TAU

0x3

Set the CIC decimator factor

(3) SUBBAND_FLL_SB_FLL_PH_4_N8

(3) SUBBAND_FLL_SB_FLL_PH_4_N8

0x0

Phases in the frequency detector

(2:0) SUBBAND_FLL_SB_FLL_WAIT

(2:0) SUBBAND_FLL_SB_FLL_WAIT

0x3

Set the number of CIC samples before stopping the FLL

0x400408D0

RF0_REG34

(29:24) CLK_RECOVERY_CLK_RECOV_CORR

(29:24) CLK_RECOVERY_CLK_RECOV_CORR

0x4

Number of samples that covers the clock recovery correlator

(23:16) CLK_RECOVERY_CLK_AB_LIMIT

(23:16) CLK_RECOVERY_CLK_AB_LIMIT

0x80

Time constant for switch the clock phase if chosen wrong in clk recovery algorithm

(15) TX_PRE_DIST_EN_PRE_DIST

(15) TX_PRE_DIST_EN_PRE_DIST

0x1

Tx pre-distortion filter (banked)

(13:8) TX_PRE_DIST_PRE_DIST_B0

(13:8) TX_PRE_DIST_PRE_DIST_B0

0x2E

Coefficient b0 of the Tx pre-distortion filter (banked)

(5:0) TX_PRE_DIST_PRE_DIST_A0

(5:0) TX_PRE_DIST_PRE_DIST_A0

0x2F

Coefficient a0 of the Tx pre-distortion filter (banked)

0x400408D4

RF0_BLE_LR

(30:24) BLR_SYNC_THRESHOLD_BLE_SYNC_THR

(30:24) BLR_SYNC_THRESHOLD_BLE_SYNC_THR

0x38

Threshold for the BLR sync word detector

(19:16) BLR_PREAMBLE_BLE_PRE_THR

(19:16) BLR_PREAMBLE_BLE_PRE_THR

0x1

Threshold for the BLR preamble detector

(15) BLE_LONG_RANGE_BLR_PUT_RI_FIFO

(15) BLE_LONG_RANGE_BLR_PUT_RI_FIFO

0x1

During the reception the RI (rate indicator) is put into the Rx FIFO (banked)

(14) BLE_LONG_RANGE_BLR500_NO_ROUGH

(14) BLE_LONG_RANGE_BLR500_NO_ROUGH

0x1

Rough recovery is stopped during the 500kbps payloads of BLR packets (banked)

(13) BLE_LONG_RANGE_BLR_LIN_FILTER

(13) BLE_LONG_RANGE_BLR_LIN_FILTER

0x1

Matched filter (banked)

(12) BLE_LONG_RANGE_EN_BLR_FLUSH

(12) BLE_LONG_RANGE_EN_BLR_FLUSH

0x1

Viterbi path 0 flushing at the end of the packet (banked)

(11) BLE_LONG_RANGE_BLR_USE_EXT_LEN

(11) BLE_LONG_RANGE_BLR_USE_EXT_LEN

0x0

BLR_PKT_LEN for flushing out the Viterbi (banked)

(10) BLE_LONG_RANGE_DISABLE_BLR_TX

(10) BLE_LONG_RANGE_DISABLE_BLR_TX

0x0

Long Range feature in Tx mode (banked)

(9) BLE_LONG_RANGE_BLR_500_N125

(9) BLE_LONG_RANGE_BLR_500_N125

0x0

Data rate selection (banked)

(8) BLE_LONG_RANGE_EN_BLR

(8) BLE_LONG_RANGE_EN_BLR

0x0

BLE long range mode (banked)

(4) HW_TRIGGER_HW_TRIG_GPIO

(4) HW_TRIGGER_HW_TRIG_GPIO

0x0

HW trigger is mapped on the GPIO instead of the Tx_on signal 0x0

(3) HW_TRIGGER_HW_TRIG_SUBBAND

(3) HW_TRIGGER_HW_TRIG_SUBBAND

0x0

Activate the sub-band selection during the Tx activation

(2) HW_TRIGGER_HW_TRIG_TX_NRX

(2) HW_TRIGGER_HW_TRIG_TX_NRX

0x0

Activate the Tx mode

(1) HW_TRIGGER_HW_TRIG_LOW

(1) HW_TRIGGER_HW_TRIG_LOW

0x0

Set the trigger polarity

(0) HW_TRIGGER_HW_TRIG_ACTIVE

(0) HW_TRIGGER_HW_TRIG_ACTIVE

0x0

Enable HW trigger

0x400408D8

RF0_REG36

(30:28) IQ_SPARES_EN_BIAS_SPARE

(30:28) IQ_SPARES_EN_BIAS_SPARE

0x0

Enable for IQ spares

(27:24) IQ_SPARES_IQ_SPARE_2

(27:24) IQ_SPARES_IQ_SPARE_2

0x0

Spare bias 2

(23:20) IQ_SPARES_IQ_SPARE_1

(23:20) IQ_SPARES_IQ_SPARE_1

0x0

Spare bias 1

(19:16) IQ_SPARES_IQ_SPARE_0

(19:16) IQ_SPARES_IQ_SPARE_0

0x0

Spare bias 0

(8) MISC_ISO_VDDA

(8) MISC_ISO_VDDA

0x0

Isolate VDDA signals

(5) BLR_DEMAPPER_BLR_SEND_DECODED_RI

(5) BLR_DEMAPPER_BLR_SEND_DECODED_RI

0x0

Fully decode the rate indicator

(4) BLR_DEMAPPER_BLR_USE_EXT_VIT_GFSK

(4) BLR_DEMAPPER_BLR_USE_EXT_VIT_GFSK

0x1

500kbps BLR uses the Viterbi GFSK decision

(3:2) BLR_DEMAPPER_BLR_500_DPHASE

(3:2) BLR_DEMAPPER_BLR_500_DPHASE

0x3

Set the distance between samples for the phase to frequency conversion in S2 mode

(1) BLR_DEMAPPER_BLR_500_LOW_GAIN

(1) BLR_DEMAPPER_BLR_500_LOW_GAIN

0x0

Set the low gain in S2 mode

(0) BLR_DEMAPPER_BLR_125_LOW_GAIN

(0) BLR_DEMAPPER_BLR_125_LOW_GAIN

0x0

Set the low gain in S8 mode

0x400408DC

RF0_PROT_TIMER

(31) PROT_TIMER_CONF_EN_PROT_TIMER

(31) PROT_TIMER_CONF_EN_PROT_TIMER

0x0

Enable the protocol timer

(29:27) PROT_TIMER_CONF_PT_T_STP_1

(29:27) PROT_TIMER_CONF_PT_T_STP_1

0x0

Configure the time stamp 1

(26:24) PROT_TIMER_CONF_PT_T_STP_0

(26:24) PROT_TIMER_CONF_PT_T_STP_0

0x0

Configure the time stamp 0

(22) STAGING_PS_NZ_START_BIT

(22) STAGING_PS_NZ_START_BIT

0x0

Select the frequency offset

(21) STAGING_PS_NZ_START

(21) STAGING_PS_NZ_START

0x0

Start the pulse shaper with a +/- 250 kHz frequency offset

(20) STAGING_DEL_PA_RAMPDW

(20) STAGING_DEL_PA_RAMPDW

0x0

Delay the PA ramp-down by 4.5 us

(19) STAGING_PEAK_DET_TH_SHIFT

(19) STAGING_PEAK_DET_TH_SHIFT

0x0

Peak detector threshold shift

(18:17) STAGING_AGC_DERIV_LVL

(18:17) STAGING_AGC_DERIV_LVL

0x2

Select the AGC derivative level

(16) STAGING_AGC_USE_DERIV

(16) STAGING_AGC_USE_DERIV

0x0

AGC algorithm uses the derivative information to accelerate the AGC settling

(15:8) BLE_DTM_BLE_DTM_LEN

(15:8) BLE_DTM_BLE_DTM_LEN

0x25

Set the BLE DTM packet length

(7) BLE_DTM_EN_BLE_DTM

(7) BLE_DTM_EN_BLE_DTM

0x0

Enable the BLE DTM automatic packets

(3:0) BLE_DTM_BLE_DTM_PKT_TYPE

(3:0) BLE_DTM_BLE_DTM_PKT_TYPE

0x0

Set the BLE DTM packet type (see Bluetooth specification)

0x400408E0

RF0_CTE_OPTS

(29) CTE_OPTS_RECT_PS_CTE

(29) CTE_OPTS_RECT_PS_CTE

0x0

Use rectangular pulse shape during the CTE

(28) CTE_OPTS_USE_CTE_WO_CP

(28) CTE_OPTS_USE_CTE_WO_CP

0x0

Enable the CTE without reading or inserting the CP

(27) CTE_OPTS_CTE_AMPL

(27) CTE_OPTS_CTE_AMPL

0x0

Enable the usage of the RSSI values to adapt the amplitude of the IQ signal based to the RSSI value

(26) CTE_OPTS_DF_AOA_SLOT_TIME

(26) CTE_OPTS_DF_AOA_SLOT_TIME

0x0

Indicate the switching/sampling slot period for AoA

(25) CTE_OPTS_CP_INSERT

(25) CTE_OPTS_CP_INSERT

0x0

Force the CP bit in the packet header to 1

(24) CTE_OPTS_EN_READ_CP

(24) CTE_OPTS_EN_READ_CP

0x0

CP bit is read in the packet header (BLE standard)

(23:16) CTE_OPTS_CTE_INFO

(23:16) CTE_OPTS_CTE_INFO

0x0

Set the CTEInfo field in the packet header while cp_insert is set to 1

(14:10) ASK_MOD_ASK_MAX

(14:10) ASK_MOD_ASK_MAX

0xC

Set the maximum value for the ASK modulation

(9:5) ASK_MOD_ASK_MIN

(9:5) ASK_MOD_ASK_MIN

0x0

Set the minimum value for the ASK modulation

(4:1) ASK_MOD_ASK_CNT

(4:1) ASK_MOD_ASK_CNT

0x7

Set the how long to count for the ASK modulation

(0) ASK_MOD_EN_RSSI_ASK

(0) ASK_MOD_EN_RSSI_ASK

0x0

PA will perform an ASK modulation

0x400408E4

RF0_PT_DELTA_0

(31:30) PT_DELTA_TS_0_PT_DELTA_T0_MULT

(31:30) PT_DELTA_TS_0_PT_DELTA_T0_MULT

0x0

Multiplier for the delta t0

(19:0) PT_DELTA_TS_0_PT_DELTA_T0

(19:0) PT_DELTA_TS_0_PT_DELTA_T0

0x0

Delta t0 for the protocol timer

0x400408E8

RF0_PT_DELTA_1

(31:30) PT_DELTA_TS_1_PT_DELTA_T1_MULT

(31:30) PT_DELTA_TS_1_PT_DELTA_T1_MULT

0x0

Multiplier for the delta t1

(19:0) PT_DELTA_TS_1_PT_DELTA_T1

(19:0) PT_DELTA_TS_1_PT_DELTA_T1

0x0

Delta t1 for the protocol timer

0x400408EC

RF0_CTE_IF

(25:16) CTE_CTRL_DELAY_TX_DF_DELAY_TX

(25:16) CTE_CTRL_DELAY_TX_DF_DELAY_TX

0x0

Delay (in 62.5ns) form the serializer up to the antenna in direction finding (banked)

(15) ANTENNA_CONF_DF_IND_PATTERN

(15) ANTENNA_CONF_DF_IND_PATTERN

0x0

Separate the antenna switching pattern from the reference one

(14) ANTENNA_CONF_DF_IND_ANTENNA

(14) ANTENNA_CONF_DF_IND_ANTENNA

0x0

Make the antenna for DF independent from the rest of the packet

(13:8) ANTENNA_CONF_ANT_LUT_M

(13:8) ANTENNA_CONF_ANT_LUT_M

0x0

Number of states used (-1) in the antenna LUT

(5) CTE_AUTO_PULL_EXT_IQ_SMP_TYPE

(5) CTE_AUTO_PULL_EXT_IQ_SMP_TYPE

0x0

Select the external IQ sample signal qualifier type

(4) CTE_AUTO_PULL_IQ_MSB

(4) CTE_AUTO_PULL_IQ_MSB

0x0

Select which signal is sent over the MSB in case of a 16bits buffers

(3:2) CTE_AUTO_PULL_IQ_DATA_BUS_SIZE

(3:2) CTE_AUTO_PULL_IQ_DATA_BUS_SIZE

0x0

Select the bus data size of IQ signals

(1) CTE_AUTO_PULL_CTE_QUAL

(1) CTE_AUTO_PULL_CTE_QUAL

0x0

Select the CTE data qualifier

(0) CTE_AUTO_PULL_EN_CTE_AUTO_PULL

(0) CTE_AUTO_PULL_EN_CTE_AUTO_PULL

0x0

Enable the automatic push of CTE data to an external IP

0x400408F0

RF0_CTE_CTRL

(25:16) CTE_CTRL_DELAY_RX_DF_DELAY_SWITCH_RX

(25:16) CTE_CTRL_DELAY_RX_DF_DELAY_SWITCH_RX

0x0

Delay (in 62.5ns) from the antenna up to the deserializer in direction finding (banked)

(9:0) CTE_CTRL_DELAY_RX_DF_DELAY_SAMPLE_RX

(9:0) CTE_CTRL_DELAY_RX_DF_DELAY_SAMPLE_RX

0x0

Delay (in 62.5ns) from the matched filter up to the deserializer in direction finding (banked)

0x400408F4

RF0_AGC_ADVANCED

(26:16) AGC_SWITCHES_AGC_SHORTS_LUT

(26:16) AGC_SWITCHES_AGC_SHORTS_LUT

0x0

Array of values that indicates if the highpass shorts must be set for the AGC state passage from n -> n+1

(8) DEBUG_FAKE_IQ_SAMPLES

(8) DEBUG_FAKE_IQ_SAMPLES

0x0

Generate fake IQ samples

(7:4) AGC_ADVANCED_AGC_TAU_SHORTS

(7:4) AGC_ADVANCED_AGC_TAU_SHORTS

0x0

Time constant that indicates the time that shorts must be on

(3) AGC_ADVANCED_AGC_EN_SHORT_PHADC

(3) AGC_ADVANCED_AGC_EN_SHORT_PHADC

0x0

Enable the short on the phase ADC highpass filter

(2) AGC_ADVANCED_AGC_EN_SHORT_IFA

(2) AGC_ADVANCED_AGC_EN_SHORT_IFA

0x0

Enable the short on the IFA highpass filter

(1) AGC_ADVANCED_AGC_USE_SHORTS

(1) AGC_ADVANCED_AGC_USE_SHORTS

0x0

Enable the usage of the shorts located in the BB path

(0) AGC_ADVANCED_AGC_FULL_SPEED

(0) AGC_ADVANCED_AGC_FULL_SPEED

0x0

Enable the maximum speed in AGC

0x400408F8

RF0_DATA_STREAMING

(9) DATA_STREAMING_DMA_PHASE_TYPE

(9) DATA_STREAMING_DMA_PHASE_TYPE

0x0

Use the phase after the rescaler instead of the raw phase from phase ADC (banked)

(8) DATA_STREAMING_DMA_EN_BUS

(8) DATA_STREAMING_DMA_EN_BUS

0x0

Enable the DMA bus on the IP interface (banked)

(6) DATA_STREAMING_PERIODIC_SAMPLE_AFTER_CTE

(6) DATA_STREAMING_PERIODIC_SAMPLE_AFTER_CTE

0x1

Restart sampling after the CTE period (banked)

(5) DATA_STREAMING_PERIODIC_SAMPLE_AT_SYNC

(5) DATA_STREAMING_PERIODIC_SAMPLE_AT_SYNC

0x0

Start sampling at the sync detection signal from the delay line (banked)

(4) DATA_STREAMING_PERIODIC_SAMPLE_OSR_CLK

(4) DATA_STREAMING_PERIODIC_SAMPLE_OSR_CLK

0x0

Oversample (8x) the reference clock of the periodic sample (banked)

(3:1) DATA_STREAMING_PERIODIC_SAMPLE_OSR

(3:1) DATA_STREAMING_PERIODIC_SAMPLE_OSR

0x3

Division factor (-1) of for the sampling period of the periodic IQ sampling (banked)

(0) DATA_STREAMING_PERIODIC_SAMPLE_EN_IQ

(0) DATA_STREAMING_PERIODIC_SAMPLE_EN_IQ

0x0

Sample periodically I and Q channels after the matched filter and put into the IQ FIFO (banked)

0x400408FC

RF0_REVISION

-

(31:24) CHIP_ID

0x30

Remapped register of CHIP_ID

0x40040900

RF0_FSM_CTRL

-

(31:30) RXFIFO_STATUS_RX_BIST_ERRORS

0x0

Rx FIFO BIST result

(31:25) RXFIFO_STATUS_RX_BIST

-

N/A

Start the bist test on the Rx FIFO (code 0x5d)

-

(29) RXFIFO_STATUS_RX_NEAR_UNDERFLOW

0x0

Rx FIFO near underflow

-

(28) RXFIFO_STATUS_RX_NEAR_OVERFLOW

0x0

Rx FIFO near overflow

-

(27) RXFIFO_STATUS_RX_UNDERFLOW

0x0

Rx FIFO underflow

-

(26) RXFIFO_STATUS_RX_OVERFLOW

0x0

Rx FIFO overflow

-

(25) RXFIFO_STATUS_RX_FULL

0x0

Rx FIFO full

-

(24) RXFIFO_STATUS_RX_EMPTY

0x0

Rx FIFO empty

(24) RXFIFO_STATUS_RX_FLUSH

-

N/A

Rx FIFO flush

-

(23:22) TXFIFO_STATUS_TX_BIST_ERRORS

0x0

Tx FIFO BIST result

(23:17) TXFIFO_STATUS_TX_BIST

-

N/A

Start the bist test on the Tx FIFO (code 0x5d)

-

(21) TXFIFO_STATUS_TX_NEAR_UNDERFLOW

0x0

Tx FIFO near underflow

-

(20) TXFIFO_STATUS_TX_NEAR_OVERFLOW

0x0

Tx FIFO near overflow

-

(19) TXFIFO_STATUS_TX_UNDERFLOW

0x0

Tx FIFO underflow

-

(18) TXFIFO_STATUS_TX_OVERFLOW

0x0

Tx FIFO overflow

-

(17) TXFIFO_STATUS_TX_FULL

0x0

Tx FIFO full

-

(16) TXFIFO_STATUS_TX_EMPTY

0x0

Tx FIFO empty

(16) TXFIFO_STATUS_TX_FLUSH

-

N/A

Tx FIFO flush

-

(10) FSM_STATUS_TX_NRX

0x0

Select Rx or Tx mode

-

(9:8) FSM_STATUS_STATUS

0x0

Status of the FSM

(3) FSM_MODE_RESET

-

N/A

FSM reset

-

(2) FSM_MODE_RX_MODE

0x0

Rx status

(2) FSM_MODE_TX_NRX

-

N/A

Set the radio in Tx or Rx mode

-

(1) FSM_MODE_TX_MODE

0x0

Tx status

(1:0) FSM_MODE_MODE

-

N/A

Set the FSM mode

-

(0) FSM_MODE_N_IDLE

0x0

FSM status

0x40040904

RF0_IQFIFO_STATUS

-

(24:16) TXFIFO_COUNT_TX_COUNT

0x0

Number of bytes in the Tx FIFO

-

(15:8) IQFIFO_COUNT_IQ_COUNT

0x0

Number of bytes in the IQ FIFO

-

(7:6) IQFIFO_STATUS_IQ_BIST_ERRORS

0x0

IQ FIFO BIST result

(7:1) IQFIFO_STATUS_IQ_BIST

-

N/A

Start the BIST test on the IQ FIFO (code 0x5d)

-

(5) IQFIFO_STATUS_IQ_NEAR_UNDERFLOW

0x0

IQ FIFO near underflow

-

(4) IQFIFO_STATUS_IQ_NEAR_OVERFLOW

0x0

IQ FIFO near overflow

-

(3) IQFIFO_STATUS_IQ_UNDERFLOW

0x0

IQ FIFO underflow

-

(2) IQFIFO_STATUS_IQ_OVERFLOW

0x0

IQ FIFO overflow

-

(1) IQFIFO_STATUS_IQ_FULL

0x0

IQ FIFO full

-

(0) IQFIFO_STATUS_IQ_EMPTY

0x0

IQ FIFO empty

(0) IQFIFO_STATUS_FLUSH

-

N/A

IQ FIFO flush

0x40040908

RF0_TXFIFO

(7:0) TXFIFO_TX_DATA

-

N/A

Data to be sent

0x4004090C

RF0_RXFIFO

-

(7:0) RXFIFO_RX_DATA

0x0

Received data

0x40040910

RF0_IQFIFO

-

(7:0) IQFIFO_IQ_DATA

0x0

IQ data for AoA or AoD

0x40040914

RF0_REG45

-

(25:16) RSSI_AVG_RSSI_AVG

0x0

Filtered RSSI value

-

(8:0) RXFIFO_COUNT_RX_COUNT

0x0

Number of bytes in the Rx FIFO

0x40040918

RF0_DESER_STATUS

-

(7) DESER_STATUS_SIGNAL_RECEIVING

0x0

Deserializer enabling

-

(6) DESER_STATUS_SYNC_DETECTED

0x0

Sync word detection

-

(5) DESER_STATUS_WAIT_SYNC

0x0

Deserializer waiting for the sync word

-

(4) DESER_STATUS_IS_ADDRESS_BR

0x0

Received address

-

(3) DESER_STATUS_PKT_LEN_ERR

0x0

Packet length

-

(2) DESER_STATUS_ADDRESS_ERR

0x0

Address error

-

(1) DESER_STATUS_CRC_ERR

0x0

CRC error

-

(0) DESER_STATUS_DESER_FINISH

0x0

Deserializer status

0x4004091C

RF0_BLE_AEC_CCM

-

(2) BLE_AES_CCM_BLE_AES_MIC_OK

0x0

AES CCM MIC error

-

(1) BLE_AES_CCM_BLE_AES_DONE_RX

0x0

AES CCM packet decoding

-

(0) BLE_AES_CCM_BLE_AES_DONE_TX

0x0

AES CCM packet encoding

0x40040920

RF0_IRQ_STATUS

-

(5) IRQ_STATUS_FLAG_RXFIFO

0x0

IRQ RXFIFO status

-

(4) IRQ_STATUS_FLAG_TXFIFO

0x0

IRQ TXFIFO status

-

(3) IRQ_STATUS_FLAG_SYNC

0x0

IRQ SYNC status

-

(2) IRQ_STATUS_FLAG_RECEIVED

0x0

IRQ RECEIVED status

-

(1) IRQ_STATUS_FLAG_RXSTOP

0x0

IRQ RXSTOP status

-

(0) IRQ_STATUS_FLAG_TX

0x0

IRQ Tx status

0x40040924

RF0_RSSI_MIN_MAX

-

(25:16) RSSI_MAX_RSSI_MAX

0x0

Maximum RSSI value over a filtering period

-

(9:0) RSSI_MIN_RSSI_MIN

0x0

Minimum RSSI value over a filtering period

0x40040928

RF0_REG4A

-

(30:28) RX_ATT_LEVEL_RX_ATT_LEVEL_PKT_LVL

0x0

Rx attenuation level (AGC level) during the packet reception

-

(26:24) RX_ATT_LEVEL_RX_ATT_LEVEL

0x0

Rx attenuation level (AGC level)

-

(23:16) DR_ERR_IND_DR_ERR_IND

0x0

Data-rate error indicator

-

(9:0) RSSI_PKT_RSSI_PKT

0x0

Filtered RSSI value sampled during the packet reception

0x4004092C

RF0_FEI

-

(31:16) FEI_PKT_FEI_PKT

0x0

Frequency error indicator sampled during the packet reception

-

(15:0) FEI_FEI_OUT

0x0

Frequency error indicator

0x40040930

RF0_REG4C

-

(31:24) LINK_QUAL_PKT_LINK_QUALITY_PKT

0x0

Link quality indicator sampled during the packet reception

-

(23:16) LINK_QUAL_LINK_QUALITY

0x0

Instantaneous link quality indicator

-

(15:0) FEI_AFC_FEI_AFC

0x0

Frequency error indicator sampled during the AFC

0x40040934

RF0_ANALOG_INFO

(25:24) BLR_READOUT_BLR_RATE

-

N/A

Bluetooth LE long range rate indicator

-

(22:20) PEAK_DET_VAL_PEAK_DET_FILT

0x0

Distance from the subband center (only available with the FLL method)

-

(18:16) PEAK_DET_VAL_PEAK_DET_RAW

0x0

Distance from the subband center (only available with the FLL method)

-

(15) ANALOG_INFO_POR_VDDA

0x0

VDDA LDO disable status

-

(14) ANALOG_INFO_PLL_UNLOCK

0x0

PLL unlock status

-

(13) ANALOG_INFO_XTAL_FINISH

0x0

XTAL algorithm status

-

(12) ANALOG_INFO_DLL_LOCKED

0x0

DLL lock status

-

(11) ANALOG_INFO_CLK_DIG_READY

0x0

Ready signal of the digital clock

-

(10) ANALOG_INFO_CLK_PLL_READY

0x0

PLL clock status

-

(9:8) ANALOG_INFO_SUBBAND

0x0

Status of the subband comparator Hi

-

(7:0) SUBBAND_ERR_SB_FLL_ERR

0x0

Distance from the subband center (only available with the FLL method)

0x40040938

RF0_SAMPLE_RSSI

(0) SAMPLE_RSSI

-

N/A

Sample the thermometric RSSI

0x4004093C

RF0_RSSI_THERM

-

(29:0) RSSI_THERM

0x0

Thermometric value of the RSSI

0x40040980

RF0_LUT_ANTENNA_ARRAY_1

(31:28) LUT_ANTENNA_ARRAY_1_ANTENNA_7

(31:28) LUT_ANTENNA_ARRAY_1_ANTENNA_7

0x0

Antenna 7 specification

(27:24) LUT_ANTENNA_ARRAY_1_ANTENNA_6

(27:24) LUT_ANTENNA_ARRAY_1_ANTENNA_6

0x0

Antenna 6 specification

(23:20) LUT_ANTENNA_ARRAY_1_ANTENNA_5

(23:20) LUT_ANTENNA_ARRAY_1_ANTENNA_5

0x0

Antenna 5 specification

(19:16) LUT_ANTENNA_ARRAY_1_ANTENNA_4

(19:16) LUT_ANTENNA_ARRAY_1_ANTENNA_4

0x0

Antenna 4 specification

(15:12) LUT_ANTENNA_ARRAY_1_ANTENNA_3

(15:12) LUT_ANTENNA_ARRAY_1_ANTENNA_3

0x3

Antenna 3 specification

(11:8) LUT_ANTENNA_ARRAY_1_ANTENNA_2

(11:8) LUT_ANTENNA_ARRAY_1_ANTENNA_2

0x2

Antenna 2 specification

(7:4) LUT_ANTENNA_ARRAY_1_ANTENNA_1

(7:4) LUT_ANTENNA_ARRAY_1_ANTENNA_1

0x1

Antenna 1 specification

(3:0) LUT_ANTENNA_ARRAY_1_ANTENNA_0

(3:0) LUT_ANTENNA_ARRAY_1_ANTENNA_0

0x0

Antenna 0 specification

0x40040984

RF0_LUT_ANTENNA_ARRAY_2

(31:28) LUT_ANTENNA_ARRAY_2_ANTENNA_15

(31:28) LUT_ANTENNA_ARRAY_2_ANTENNA_15

0x0

Antenna 15 specification

(27:24) LUT_ANTENNA_ARRAY_2_ANTENNA_14

(27:24) LUT_ANTENNA_ARRAY_2_ANTENNA_14

0x0

Antenna 14 specification

(23:20) LUT_ANTENNA_ARRAY_2_ANTENNA_13

(23:20) LUT_ANTENNA_ARRAY_2_ANTENNA_13

0x0

Antenna 13 specification

(19:16) LUT_ANTENNA_ARRAY_2_ANTENNA_12

(19:16) LUT_ANTENNA_ARRAY_2_ANTENNA_12

0x0

Antenna 12 specification

(15:12) LUT_ANTENNA_ARRAY_2_ANTENNA_11

(15:12) LUT_ANTENNA_ARRAY_2_ANTENNA_11

0x0

Antenna 11 specification

(11:8) LUT_ANTENNA_ARRAY_2_ANTENNA_10

(11:8) LUT_ANTENNA_ARRAY_2_ANTENNA_10

0x0

Antenna 10 specification

(7:4) LUT_ANTENNA_ARRAY_2_ANTENNA_9

(7:4) LUT_ANTENNA_ARRAY_2_ANTENNA_9

0x0

Antenna 9 specification

(3:0) LUT_ANTENNA_ARRAY_2_ANTENNA_8

(3:0) LUT_ANTENNA_ARRAY_2_ANTENNA_8

0x0

Antenna 8 specification

0x40040988

RF0_LUT_ANTENNA_ARRAY_3

(31:28) LUT_ANTENNA_ARRAY_3_ANTENNA_23

(31:28) LUT_ANTENNA_ARRAY_3_ANTENNA_23

0x0

Antenna 23 specification

(27:24) LUT_ANTENNA_ARRAY_3_ANTENNA_22

(27:24) LUT_ANTENNA_ARRAY_3_ANTENNA_22

0x0

Antenna 22 specification

(23:20) LUT_ANTENNA_ARRAY_3_ANTENNA_21

(23:20) LUT_ANTENNA_ARRAY_3_ANTENNA_21

0x0

Antenna 21 specification

(19:16) LUT_ANTENNA_ARRAY_3_ANTENNA_20

(19:16) LUT_ANTENNA_ARRAY_3_ANTENNA_20

0x0

Antenna 20 specification

(15:12) LUT_ANTENNA_ARRAY_3_ANTENNA_19

(15:12) LUT_ANTENNA_ARRAY_3_ANTENNA_19

0x0

Antenna 19 specification

(11:8) LUT_ANTENNA_ARRAY_3_ANTENNA_18

(11:8) LUT_ANTENNA_ARRAY_3_ANTENNA_18

0x0

Antenna 18 specification

(7:4) LUT_ANTENNA_ARRAY_3_ANTENNA_17

(7:4) LUT_ANTENNA_ARRAY_3_ANTENNA_17

0x0

Antenna 17 specification

(3:0) LUT_ANTENNA_ARRAY_3_ANTENNA_16

(3:0) LUT_ANTENNA_ARRAY_3_ANTENNA_16

0x0

Antenna 16 specification

0x4004098C

RF0_LUT_ANTENNA_ARRAY_4

(31:28) LUT_ANTENNA_ARRAY_4_ANTENNA_31

(31:28) LUT_ANTENNA_ARRAY_4_ANTENNA_31

0x0

Antenna 31 specification

(27:24) LUT_ANTENNA_ARRAY_4_ANTENNA_30

(27:24) LUT_ANTENNA_ARRAY_4_ANTENNA_30

0x0

Antenna 30 specification

(23:20) LUT_ANTENNA_ARRAY_4_ANTENNA_29

(23:20) LUT_ANTENNA_ARRAY_4_ANTENNA_29

0x0

Antenna 29 specification

(19:16) LUT_ANTENNA_ARRAY_4_ANTENNA_28

(19:16) LUT_ANTENNA_ARRAY_4_ANTENNA_28

0x0

Antenna 28 specification

(15:12) LUT_ANTENNA_ARRAY_4_ANTENNA_27

(15:12) LUT_ANTENNA_ARRAY_4_ANTENNA_27

0x0

Antenna 27 specification

(11:8) LUT_ANTENNA_ARRAY_4_ANTENNA_26

(11:8) LUT_ANTENNA_ARRAY_4_ANTENNA_26

0x0

Antenna 26 specification

(7:4) LUT_ANTENNA_ARRAY_4_ANTENNA_25

(7:4) LUT_ANTENNA_ARRAY_4_ANTENNA_25

0x0

Antenna 25 specification

(3:0) LUT_ANTENNA_ARRAY_4_ANTENNA_24

(3:0) LUT_ANTENNA_ARRAY_4_ANTENNA_24

0x0

Antenna 24 specification

0x400409C0

RF0_REG50

-

(27) FEATURES_HAS_BLE_AES

0x0

Bluetooth AES block availability

-

(26) FEATURES_HAS_BLE_DF_AOA_AOD

0x1

Bluetooth Direction Finding AoA/AoD feature availability

-

(25) FEATURES_HAS_BLE_LONG_RANGE

0x1

Bluetooth long range feature availability

-

(24) FEATURES_FEATURES_AVAILABLE

0x1

Features availability

(23:16) BLR_PKT_LEN_BLR_PKT_LEN

-

N/A

Packet length of the BLR packet

(15:8) PROT_TIMER_PT_CMD

-

N/A

Protocol timer command

(0) COMMANDS_START_SUBBAND

-

N/A

Subband selection algorithm

0x400409E0

RF0_REG51

(31:24) FSM_MODE_RM_TX

(31:24) FSM_MODE_RM_TX

0x0

Remapped register of FSM_MODE

(23:16) PA_PWR_RM

(23:16) PA_PWR_RM

0x0

Remapped register of PA_PWR

(15:8) CHANNEL_RM_TX

(15:8) CHANNEL_RM_TX

0x0

Remapped register of CHANNEL

(7:0) RATE_TX

(7:0) RATE_TX

0x0

Remapped register of BANK

0x400409E8

RF0_REG52

(31:24) ACCESS_ADDRESS

(31:24) ACCESS_ADDRESS

0x0

Remapped register of PATTERN

(23:16) FSM_MODE_RM_RX

(23:16) FSM_MODE_RM_RX

0x0

Remapped register of FSM_MODE

(15:8) CHANNEL_RM_RX

(15:8) CHANNEL_RM_RX

0x0

Remapped register of CHANNEL

(7:0) RATE_RX

(7:0) RATE_RX

0x0

Remapped register of BANK

0x400409F0

RF0_REG53

-

(23:16) RSSI_MAX_RM

0x0

Remapped register of RSSI_MAX

-

(15:8) RSSI_MIN_RM

0x0

Remapped register of RSSI_MIN

-

(7:0) RSSI_AVG_RM

0x0

Remapped register of RSSI_AVG

0x400409F4

RF0_REG54

(7:0) BLR_PACKET_LEN

-

N/A

Remapped register of BLR_PACKET_LEN

0x400409F8

RF0_REG55

-

(7:0) ITRX_FEATURES

0x0

Remapped register of ITRX_FEATURES

0x400409FC

RF0_REG56

-

(31:24) CHIP_ID_CHIP_ID

0x30

Version of the chip

-

(23:16) MD5_REGS_MD5_REGS

0x0

MD5 calculated on the register map file

(15:8) SCAN_2_SCAN_2_PASSWORD

-

N/A

SCAN 2 key

(7:0) SCAN_1_SCAN_1_PASSWORD

-

N/A

SCAN 1 key

0x40040A00

RF1_REG00

(31) DATAWHITE_BTLE_DW_BTLE

(31) DATAWHITE_BTLE_DW_BTLE

0x1

Data whitening control

(30:24) DATAWHITE_BTLE_DW_BTLE_RST

(30:24) DATAWHITE_BTLE_DW_BTLE_RST

0x0

Reset value to put on the Bluetooth LE data whitening shift register

(23) FOURFSK_CODING_EN_FOURFSK_CODING

(23) FOURFSK_CODING_EN_FOURFSK_CODING

0x0

Enable 4FSK coding

(22:20) FOURFSK_CODING_TX_FOURFSK_CODING

(22:20) FOURFSK_CODING_TX_FOURFSK_CODING

0x0

Set the 4FSK coding (Tx mode)

(18:16) FOURFSK_CODING_RX_FOURFSK_CODING

(18:16) FOURFSK_CODING_RX_FOURFSK_CODING

0x0

Set the 4FSK decoding (Rx mode)

(14) MODE2_DIFF_CODING

(14) MODE2_DIFF_CODING

0x0

Differential coding/decoding

(13) MODE2_PSK_NFSK

(13) MODE2_PSK_NFSK

0x0

FSK/PSK mode selection

(12:8) MODE2_TESTMODE

(12:8) MODE2_TESTMODE

0x0

Output test mode

(7) MODE_NOT_TO_IDLE

(7) MODE_NOT_TO_IDLE

0x0

FSM goes in suspend mode after a Tx or Rx packet

(5) MODE_EN_FSM

(5) MODE_EN_FSM

0x1

Radio FSM control

(4) MODE_EN_DESERIALIZER

(4) MODE_EN_DESERIALIZER

0x0

Deserializer control

(3) MODE_EN_SERIALIZER

(3) MODE_EN_SERIALIZER

0x0

Serializer control

(2) MODE_TX_NRX

(2) MODE_TX_NRX

0x0

Select Tx or Rx mode

(1:0) MODE_MODE

(1:0) MODE_MODE

0x2

Select the working mode of the digital baseband

0x40040A04

RF1_REG01

(31:24) TAU_PHASE_RECOV_TAU_PHASE_RECOV

(31:24) TAU_PHASE_RECOV_TAU_PHASE_RECOV

0x14

Time constant of the fine carrier recovery block (banked)

(23:16) TAU_ROUGH_RECOV_TAU_ROUGH_RECOV

(23:16) TAU_ROUGH_RECOV_TAU_ROUGH_RECOV

0xB

Time constant of the rough carrier recovery block (banked)

(15) CARRIER_RECOVERY_EN_CORRECT_CFREQ_AFC

(15) CARRIER_RECOVERY_EN_CORRECT_CFREQ_AFC

0x0

Automatic AFC correction (banked)

(14) CARRIER_RECOVERY_CORRECT_CFREQ_IF_NEG

(14) CARRIER_RECOVERY_CORRECT_CFREQ_IF_NEG

0x0

IF correction (banked)

(13) CARRIER_RECOVERY_EN_CORRECT_CFREQ_IF

(13) CARRIER_RECOVERY_EN_CORRECT_CFREQ_IF

0x1

Automatic IF correction (banked)

(12) CARRIER_RECOVERY_AFC_NEG

(12) CARRIER_RECOVERY_AFC_NEG

0x0

AFC correction (banked)

(11) CARRIER_RECOVERY_STARTER_MODE

(11) CARRIER_RECOVERY_STARTER_MODE

0x0

Starter mode (banked)

(10) CARRIER_RECOVERY_EN_AFC

(10) CARRIER_RECOVERY_EN_AFC

0x0

Automatic frequency control (banked)

(9) CARRIER_RECOVERY_EN_FINE_RECOV

(9) CARRIER_RECOVERY_EN_FINE_RECOV

0x1

Fine carrier recovery (banked)

(8) CARRIER_RECOVERY_EN_ROUGH_RECOV

(8) CARRIER_RECOVERY_EN_ROUGH_RECOV

0x0

Rough carrier recovery (banked)

(6) MOD_TX_PULSE_NSYM

(6) MOD_TX_PULSE_NSYM

0x0

Tx pulse shape function

(5) MOD_TX_EN_INTERP

(5) MOD_TX_EN_INTERP

0x0

Tx CIC interpolator

(4:0) MOD_TX_CK_TX_M

(4:0) MOD_TX_CK_TX_M

0x0

Unsigned value determining the Tx CIC interpolator frequency

0x40040A08

RF1_REG02

(25:24) DATARATE_OFFSET_DR_LIMIT

(25:24) DATARATE_OFFSET_DR_LIMIT

0x0

Set the data-rate recovery limits

(23:16) DATARATE_OFFSET_DATARATE_OFFSET

(23:16) DATARATE_OFFSET_DATARATE_OFFSET

0x0

Data-rate offset

(15:8) TAU_DATARATE_RECOV_TAU_DATARATE_RECOV

(15:8) TAU_DATARATE_RECOV_TAU_DATARATE_RECOV

0x20

Time constant of the data-rate recovery

(7:0) TAU_CLK_RECOV_TAU_CLK_RECOV

(7:0) TAU_CLK_RECOV_TAU_CLK_RECOV

0x9

Time constant of the clock recovery (banked)

0x40040A0C

RF1_REG03

(31:30) MAC_CONF_MAC_TIMER_GR

(31:30) MAC_CONF_MAC_TIMER_GR

0x2

MAC timer granularity

(29) MAC_CONF_RX_MAC_ACT

(29) MAC_CONF_RX_MAC_ACT

0x0

Switch FSM to Rx or Tx mode after an Rx mode

(28) MAC_CONF_RX_MAC_TX_NRX

(28) MAC_CONF_RX_MAC_TX_NRX

0x0

Switch FSM to Tx mode after an Rx mode (Rx otherwise)

(27) MAC_CONF_RX_MAC_START_NSTOP

(27) MAC_CONF_RX_MAC_START_NSTOP

0x0

MAC timer activation after sync word detection

(26) MAC_CONF_TX_MAC_ACT

(26) MAC_CONF_TX_MAC_ACT

0x0

Switch FSM to Rx or Tx mode after a Tx mode

(25) MAC_CONF_TX_MAC_TX_NRX

(25) MAC_CONF_TX_MAC_TX_NRX

0x0

Switch FSM to Tx mode after a Tx mode (Rx otherwise)

(24) MAC_CONF_TX_MAC_START_NSTOP

(24) MAC_CONF_TX_MAC_START_NSTOP

0x0

MAC timer activation after packet transmission

(23) IRQ_CONF_IRQ_HIGH_Z

(23) IRQ_CONF_IRQ_HIGH_Z

0x0

Pads are set to high-Z when the IRQ is not active

(22) IRQ_CONF_IRQ_ACTIVE_LOW

(22) IRQ_CONF_IRQ_ACTIVE_LOW

0x1

IRQ are active low

(21:16) IRQ_CONF_IRQS_MASK

(21:16) IRQ_CONF_IRQS_MASK

0x0

Mask to determine which IRQs are enabled (active high)

(15:13) FIFO_2_FIFO_THR_TX

(15:13) FIFO_2_FIFO_THR_TX

0x0

Threshold indicating the "almost empty" Tx FIFO state

(12) FIFO_2_WAIT_TXFIFO_WR

(12) FIFO_2_WAIT_TXFIFO_WR

0x0

FSM will wait a Tx FIFO write before starting the Tx mode in case of an empty Tx FIFO

(11) FIFO_2_STOP_ON_RXFF_OVFLW

(11) FIFO_2_STOP_ON_RXFF_OVFLW

0x0

Stop the reception in case of a FIFO overflow

(10) FIFO_2_STOP_ON_TXFF_UNFLW

(10) FIFO_2_STOP_ON_TXFF_UNFLW

0x0

Stop the transmission in case of a FIFO underflow

(9) FIFO_2_RXFF_FLUSH_ON_START

(9) FIFO_2_RXFF_FLUSH_ON_START

0x1

Flush the Rx FIFO when the Rx mode is enabled in order to receive a packet with an empty FIFO

(8) FIFO_2_TXFF_FLUSH_ON_STOP

(8) FIFO_2_TXFF_FLUSH_ON_STOP

0x1

Flush the Tx FIFO after the end of a packet transmission in order to have an empty FIFO

(7) FIFO_FIFO_FLUSH_ON_OVFLW

(7) FIFO_FIFO_FLUSH_ON_OVFLW

0x0

Overflow FIFO flush control

(6) FIFO_FIFO_FLUSH_ON_ADDR_ERR

(6) FIFO_FIFO_FLUSH_ON_ADDR_ERR

0x0

Address error FIFO flush control

(5) FIFO_FIFO_FLUSH_ON_PL_ERR

(5) FIFO_FIFO_FLUSH_ON_PL_ERR

0x0

Packet length error FIFO flush control

(4) FIFO_FIFO_FLUSH_ON_CRC_ERR

(4) FIFO_FIFO_FLUSH_ON_CRC_ERR

0x1

CRC error FIFO flush control

(3) FIFO_RX_FIFO_ACK

(3) FIFO_RX_FIFO_ACK

0x0

Rx FIFO acknowledgement

(2:0) FIFO_FIFO_THR

(2:0) FIFO_FIFO_THR

0x0

Threshold indicating the "almost full" Rx FIFO state

0x40040A10

RF1_PADS_03

(28:24) PAD_CONF_1_PAD_3_CONF

(28:24) PAD_CONF_1_PAD_3_CONF

0x0

Configuration of GPIO pad 3

(20:16) PAD_CONF_1_PAD_2_CONF

(20:16) PAD_CONF_1_PAD_2_CONF

0x0

Configuration of GPIO pad 2

(12:8) PAD_CONF_1_PAD_1_CONF

(12:8) PAD_CONF_1_PAD_1_CONF

0x0

Configuration of GPIO pad 1

(4:0) PAD_CONF_1_PAD_0_CONF

(4:0) PAD_CONF_1_PAD_0_CONF

0x0

Configuration of GPIO pad 0

0x40040A14

RF1_PADS_47

(28:24) PAD_CONF_2_PAD_7_CONF

(28:24) PAD_CONF_2_PAD_7_CONF

0x0

Configuration of GPIO pad 7

(20:16) PAD_CONF_2_PAD_6_CONF

(20:16) PAD_CONF_2_PAD_6_CONF

0x0

Configuration of GPIO pad 6

(12:8) PAD_CONF_2_PAD_5_CONF

(12:8) PAD_CONF_2_PAD_5_CONF

0x0

Configuration of GPIO pad 5

(4:0) PAD_CONF_2_PAD_4_CONF

(4:0) PAD_CONF_2_PAD_4_CONF

0x0

Configuration of GPIO pad 4

0x40040A18

RF1_CENTER_FREQ

(31) CENTER_FREQ_ADAPT_CFREQ

(31) CENTER_FREQ_ADAPT_CFREQ

0x1

Frequency adaptation between Tx and Rx modes

(30) CENTER_FREQ_RX_DIV_5_N6

(30) CENTER_FREQ_RX_DIV_5_N6

0x0

Ratio of the PLL reference between Tx and Rx modes

(29:0) CENTER_FREQ_CENTER_FREQUENCY

(29:0) CENTER_FREQ_CENTER_FREQUENCY

0x215C71B

Set the center frequency

0x40040A1C

RF1_PADS_89

(31:24) TX_MAC_TIMER_TX_MAC_TIMER

(31:24) TX_MAC_TIMER_TX_MAC_TIMER

0x82

Time to wait after the Tx mode

(23:16) RX_MAC_TIMER_RX_MAC_TIMER

(23:16) RX_MAC_TIMER_RX_MAC_TIMER

0x23

Time to wait after the Rx mode

(12:8) PAD_CONF_3_PAD_9_CONF

(12:8) PAD_CONF_3_PAD_9_CONF

0x0

Configuration of GPIO pad 9

(4:0) PAD_CONF_3_PAD_8_CONF

(4:0) PAD_CONF_3_PAD_8_CONF

0x0

Configuration of GPIO pad 8

0x40040A20

RF1_REG08

(31:30) MOD_INFO_RX_DIV_CK_RX

(31:30) MOD_INFO_RX_DIV_CK_RX

0x0

Set the clock divider for the Rx mode (banked)

(29) MOD_INFO_RX_SYMBOL_2BIT_RX

(29) MOD_INFO_RX_SYMBOL_2BIT_RX

0x0

Rx symbol bits composition (banked)

(28:24) MOD_INFO_RX_DR_M_RX

(28:24) MOD_INFO_RX_DR_M_RX

0x0

Unsigned value determining the oversampling frequency and consequently the data-rate (banked)

(23:22) MOD_INFO_TX_DIV_CK_TX

(23:22) MOD_INFO_TX_DIV_CK_TX

0x0

Set the clock divider for the Tx mode (banked)

(21) MOD_INFO_TX_SYMBOL_2BIT_TX

(21) MOD_INFO_TX_SYMBOL_2BIT_TX

0x0

Tx symbol bits composition (banked)

(20:16) MOD_INFO_TX_DR_M_TX

(20:16) MOD_INFO_TX_DR_M_TX

0x0

Unsigned value determining the oversampling frequency and consequently the data-rate (banked)

(14) CHANNEL_SWITCH_IQ

(14) CHANNEL_SWITCH_IQ

0x0

Switch I and Q channels

(13:8) CHANNEL_CHANNEL

(13:8) CHANNEL_CHANNEL

0x0

Channel number

(3) BANK_DATARATE_TX_NRX

(3) BANK_DATARATE_TX_NRX

0x0

Select the data-rate register

(2) BANK_STD_BLE_RATES

(2) BANK_STD_BLE_RATES

0x0

Select the actual bank behavior

(1:0) BANK_BANK

(1:0) BANK_BANK

0x0

Select the used bank

0x40040A24

RF1_CODING

(31) CODING_EN_DATAWHITE

(31) CODING_EN_DATAWHITE

0x1

Data-whitening enabling (banked)

(30) CODING_I_NQ_DELAYED

(30) CODING_I_NQ_DELAYED

0x0

Channel I delay (banked)

(29) CODING_OFFSET

(29) CODING_OFFSET

0x0

Offset (delay) introduction (banked)

(28) CODING_BIT_INVERT

(28) CODING_BIT_INVERT

0x0

Bit value inversion in Tx and Rx modes (banked)

(27) CODING_EVEN_BEFORE_ODD

(27) CODING_EVEN_BEFORE_ODD

0x0

Determine the bit order in case of a 2 bits per symbol modulation (banked)

(26) CODING_EN_802154_L2F

(26) CODING_EN_802154_L2F

0x0

Linear to frequency encoding needed in order to modulate an OQPSK as an MSK (banked)

(25) CODING_EN_802154_B2C

(25) CODING_EN_802154_B2C

0x0

Bit to chips encoding used in the IEEE 802.15.4 standard (banked)

(24) CODING_EN_MANCHESTER

(24) CODING_EN_MANCHESTER

0x0

Manchester encoding (banked)

(23) CHANNELS_2_EN_CHANNEL_SEL

(23) CHANNELS_2_EN_CHANNEL_SEL

0x1

Definition of channels (banked)

(22) CHANNELS_2_EN_CHN_BLE

(22) CHANNELS_2_EN_CHN_BLE

0x1

BLE channels index LUT (banked)

(19:16) CHANNELS_2_CHANNEL_SPACING_HI

(19:16) CHANNELS_2_CHANNEL_SPACING_HI

0x7

Channel spacing MSB (banked)

(15:0) CHANNELS_1_CHANNEL_SPACING_LO

(15:0) CHANNELS_1_CHANNEL_SPACING_LO

0x1C72

Channel spacing LSB (banked)

0x40040A28

RF1_PACKET_HANDLING

(31:24) PREAMBLE_PREAMBLE

(31:24) PREAMBLE_PREAMBLE

0x55

Preamble to be inserted (banked)

(22) PACKET_LENGTH_OPTS_EN_PACKET_LEN_FIX

(22) PACKET_LENGTH_OPTS_EN_PACKET_LEN_FIX

0x0

Packet length configuration (banked)

(21:18) PACKET_LENGTH_OPTS_PACKET_LEN_CORR

(21:18) PACKET_LENGTH_OPTS_PACKET_LEN_CORR

0x0

Signed value specifying the correction to apply to the specified packet length (banked)

(17:16) PACKET_LENGTH_OPTS_PACKET_LEN_POS

(17:16) PACKET_LENGTH_OPTS_PACKET_LEN_POS

0x1

Unsigned value that specifies the position of the packet length after the pattern (banked)

(15:8) PACKET_LENGTH_PACKET_LEN

(15:8) PACKET_LENGTH_PACKET_LEN

0xFF

The packet length in the fixed packet length mode (banked)

(7) PACKET_HANDLING_LSB_FIRST

(7) PACKET_HANDLING_LSB_FIRST

0x1

Select LSB or MSB to send first (banked)

(6) PACKET_HANDLING_EN_CRC

(6) PACKET_HANDLING_EN_CRC

0x1

Automatic CRC evaluation and insertion (banked)

(5) PACKET_HANDLING_EN_CRC_ON_PKTLEN

(5) PACKET_HANDLING_EN_CRC_ON_PKTLEN

0x1

CRC calculation on the packet length part of the packet (banked)

(4) PACKET_HANDLING_EN_PREAMBLE

(4) PACKET_HANDLING_EN_PREAMBLE

0x1

Automatic preamble insertion (banked)

(3) PACKET_HANDLING_EN_MULTI_FRAME

(3) PACKET_HANDLING_EN_MULTI_FRAME

0x0

Multi-frame packet (banked)

(2) PACKET_HANDLING_ENB_DW_ON_CRC

(2) PACKET_HANDLING_ENB_DW_ON_CRC

0x0

Data-whitening on the CRC disabling (banked)

(1) PACKET_HANDLING_EN_PATTERN

(1) PACKET_HANDLING_EN_PATTERN

0x1

Automatic pattern insertion and recognition (banked)

(0) PACKET_HANDLING_EN_PACKET

(0) PACKET_HANDLING_EN_PACKET

0x1

Packet handler enabling (banked)

0x40040A2C

RF1_SYNC_PATTERN

(31:0) PATTERN

(31:0) PATTERN

0x8E89BED6

Pattern (sync word) to be inserted or recognized (banked)

0x40040A30

RF1_REG0C

(31:16) ADDRESS_ADDRESS

(31:16) ADDRESS_ADDRESS

0x0

Address of the node (banked)

(11) ADDRESS_CONF_ADDRESS_LEN

(11) ADDRESS_CONF_ADDRESS_LEN

0x0

Address length selection (banked)

(10) ADDRESS_CONF_EN_ADDRESS_RX_BR

(10) ADDRESS_CONF_EN_ADDRESS_RX_BR

0x0

Broadcast address detection in Rx mode (banked)

(9) ADDRESS_CONF_EN_ADDRESS_RX

(9) ADDRESS_CONF_EN_ADDRESS_RX

0x0

Address detection in Rx mode (banked)

(8) ADDRESS_CONF_EN_ADDRESS_TX

(8) ADDRESS_CONF_EN_ADDRESS_TX

0x0

Address insertion in Tx mode (banked)

(7:0) PREAMBLE_LENGTH_PREAMBLE_LEN

(7:0) PREAMBLE_LENGTH_PREAMBLE_LEN

0x0

Length of the preamble -1 (banked)

0x40040A34

RF1_PACKET_EXTRA

(29:28) CONV_CODES_CONF_STOP_WORD_LEN

(29:28) CONV_CODES_CONF_STOP_WORD_LEN

0x0

Length of the stop word (banked)

(27:26) CONV_CODES_CONF_CC_VITERBI_LEN

(27:26) CONV_CODES_CONF_CC_VITERBI_LEN

0x2

Set the memory length of the Viterbi decoder (banked)

(25) CONV_CODES_CONF_CC_EN_TX_STOP

(25) CONV_CODES_CONF_CC_EN_TX_STOP

0x0

Stop word at the end of the transmission (banked)

(24) CONV_CODES_CONF_EN_CONV_CODE

(24) CONV_CODES_CONF_EN_CONV_CODE

0x0

Convolutional codes (banked)

(22) PACKET_EXTRA_FIFO_REWIND

(22) PACKET_EXTRA_FIFO_REWIND

0x0

Rewind the FIFO to the initial stage at the end of a Tx transmission (banked)

(21) PACKET_EXTRA_BLE_PREAMBLE

(21) PACKET_EXTRA_BLE_PREAMBLE

0x1

Handle the preamble directly in Tx mode (PREAMBLE register is not used) according to the BLE standard (banked)

(20) PACKET_EXTRA_PKT_INFO_PRE_NPOST

(20) PACKET_EXTRA_PKT_INFO_PRE_NPOST

0x0

Packet information sampling (banked)

(19:18) PACKET_EXTRA_PATTERN_MAX_ERR

(19:18) PACKET_EXTRA_PATTERN_MAX_ERR

0x0

Unsigned value that specifies the maximum number of errors in the pattern recognition (banked)

(17:16) PACKET_EXTRA_PATTERN_WORD_LEN

(17:16) PACKET_EXTRA_PATTERN_WORD_LEN

0x3

Pattern word length (banked)

(15:0) ADDRESS_BROADCAST_ADDRESS_BR

(15:0) ADDRESS_BROADCAST_ADDRESS_BR

0x0

Broadcast address (banked)

0x40040A38

RF1_CRC_POLYNOMIAL

(31:0) CRC_POLY

(31:0) CRC_POLY

0x80032D

CRC polynomial (banked)

0x40040A3C

RF1_CRC_RST

(31:0) CRC_RST

(31:0) CRC_RST

0x555555

CRC reset value (banked)

0x40040A40

RF1_REG10

(25:21) CONV_CODES_PUNCT_CC_PUNCT_1

(25:21) CONV_CODES_PUNCT_CC_PUNCT_1

0x1

Puncture of the second convolutional code (banked)

(20:16) CONV_CODES_PUNCT_CC_PUNCT_0

(20:16) CONV_CODES_PUNCT_CC_PUNCT_0

0x1

Puncture of the first convolutional code (banked)

(11) FRAC_CONF_TX_FRAC_GAIN

(11) FRAC_CONF_TX_FRAC_GAIN

0x0

Additional gain for fractional data-rates in Tx mode (banked)

(10) FRAC_CONF_RX_FRAC_GAIN

(10) FRAC_CONF_RX_FRAC_GAIN

0x0

Additional gain for fractional data-rates in Rx mode (banked)

(9) FRAC_CONF_TX_EN_FRAC

(9) FRAC_CONF_TX_EN_FRAC

0x0

Fractional data-rates in Tx mode (banked)

(8) FRAC_CONF_RX_EN_FRAC

(8) FRAC_CONF_RX_EN_FRAC

0x0

Fractional data-rates in Rx mode (banked)

(7:4) CONV_CODES_POLY_CC_POLY_1

(7:4) CONV_CODES_POLY_CC_POLY_1

0xD

Second convolutional code (banked)

(3:0) CONV_CODES_POLY_CC_POLY_0

(3:0) CONV_CODES_POLY_CC_POLY_0

0xF

First convolutional code (banked)

0x40040A44

RF1_REG11

(31) FILTER_GAIN_LIN_FILTER

(31) FILTER_GAIN_LIN_FILTER

0x0

Enable the linear filtering (banked)

(30) FILTER_GAIN_LOW_LIN_GAIN

(30) FILTER_GAIN_LOW_LIN_GAIN

0x0

Reduce the total gain by two if the linear gain is set (banked)

(29:27) FILTER_GAIN_GAIN_M

(29:27) FILTER_GAIN_GAIN_M

0x0

Mantissa of the final stage gain of the matched filter (banked)

(26:24) FILTER_GAIN_GAIN_E

(26:24) FILTER_GAIN_GAIN_E

0x0

Exponent of the final stage gain of the matched filter (banked)

(23:20) TX_MULT_TX_MULT_EXP

(23:20) TX_MULT_TX_MULT_EXP

0x2

Exponent of the Tx multiplier (banked)

(19:16) TX_MULT_TX_MULT_MAN

(19:16) TX_MULT_TX_MULT_MAN

0x9

Mantissa of the Tx multiplier (banked)

(15:12) TX_FRAC_CONF_TX_FRAC_DEN

(15:12) TX_FRAC_CONF_TX_FRAC_DEN

0x0

Denominator of the fractional data-rate in Tx mode (banked)

(11:8) TX_FRAC_CONF_TX_FRAC_NUM

(11:8) TX_FRAC_CONF_TX_FRAC_NUM

0x0

Numerator of the fractional data-rate in Tx mode (banked)

(7:4) RX_FRAC_CONF_RX_FRAC_DEN

(7:4) RX_FRAC_CONF_RX_FRAC_DEN

0x0

Denominator of the fractional data-rate in Rx mode (banked)

(3:0) RX_FRAC_CONF_RX_FRAC_NUM

(3:0) RX_FRAC_CONF_RX_FRAC_NUM

0x0

Numerator of the fractional data-rate in Rx mode (banked)

0x40040A48

RF1_TX_PULSE_SHAPE_1

(31:24) TX_PULSE_SHAPE_1_TX_COEF4

(31:24) TX_PULSE_SHAPE_1_TX_COEF4

0x0

Tx pulse shape coefficient 4 (banked)

(23:16) TX_PULSE_SHAPE_1_TX_COEF3

(23:16) TX_PULSE_SHAPE_1_TX_COEF3

0x0

Tx pulse shape coefficient 3 (banked)

(15:8) TX_PULSE_SHAPE_1_TX_COEF2

(15:8) TX_PULSE_SHAPE_1_TX_COEF2

0x0

Tx pulse shape coefficient 2 (banked)

(7:0) TX_PULSE_SHAPE_1_TX_COEF1

(7:0) TX_PULSE_SHAPE_1_TX_COEF1

0x0

Tx pulse shape coefficient 1 (banked)

0x40040A4C

RF1_TX_PULSE_SHAPE_2

(31:24) TX_PULSE_SHAPE_2_TX_COEF8

(31:24) TX_PULSE_SHAPE_2_TX_COEF8

0x2

Tx pulse shape coefficient 8 (banked)

(23:16) TX_PULSE_SHAPE_2_TX_COEF7

(23:16) TX_PULSE_SHAPE_2_TX_COEF7

0x1

Tx pulse shape coefficient 7 (banked)

(15:8) TX_PULSE_SHAPE_2_TX_COEF6

(15:8) TX_PULSE_SHAPE_2_TX_COEF6

0x0

Tx pulse shape coefficient 6 (banked)

(7:0) TX_PULSE_SHAPE_2_TX_COEF5

(7:0) TX_PULSE_SHAPE_2_TX_COEF5

0x0

Tx pulse shape coefficient 5 (banked)

0x40040A50

RF1_TX_PULSE_SHAPE_3

(31:24) TX_PULSE_SHAPE_3_TX_COEF12

(31:24) TX_PULSE_SHAPE_3_TX_COEF12

0x36

Tx pulse shape coefficient 12 (banked)

(23:16) TX_PULSE_SHAPE_3_TX_COEF11

(23:16) TX_PULSE_SHAPE_3_TX_COEF11

0x20

Tx pulse shape coefficient 11 (banked)

(15:8) TX_PULSE_SHAPE_3_TX_COEF10

(15:8) TX_PULSE_SHAPE_3_TX_COEF10

0x10

Tx pulse shape coefficient 10 (banked)

(7:0) TX_PULSE_SHAPE_3_TX_COEF9

(7:0) TX_PULSE_SHAPE_3_TX_COEF9

0x7

Tx pulse shape coefficient 9 (banked)

0x40040A54

RF1_TX_PULSE_SHAPE_4

(31:24) TX_PULSE_SHAPE_4_TX_COEF16

(31:24) TX_PULSE_SHAPE_4_TX_COEF16

0x7D

Tx pulse shape coefficient 16 (banked)

(23:16) TX_PULSE_SHAPE_4_TX_COEF15

(23:16) TX_PULSE_SHAPE_4_TX_COEF15

0x75

Tx pulse shape coefficient 15 (banked)

(15:8) TX_PULSE_SHAPE_4_TX_COEF14

(15:8) TX_PULSE_SHAPE_4_TX_COEF14

0x66

Tx pulse shape coefficient 14 (banked)

(7:0) TX_PULSE_SHAPE_4_TX_COEF13

(7:0) TX_PULSE_SHAPE_4_TX_COEF13

0x4F

Tx pulse shape coefficient 13 (banked)

0x40040A58

RF1_FRONTEND

(25:16) RX_IF_DIG_IF_DIG

(25:16) RX_IF_DIG_IF_DIG

0x40

IF frequency (banked)

(14:11) FRONTEND_RESAMPLE_PH_GAIN

(14:11) FRONTEND_RESAMPLE_PH_GAIN

0x6

Gain of the phase resampling block (banked)

(10:8) FRONTEND_RESAMPLE_RSSI_G2

(10:8) FRONTEND_RESAMPLE_RSSI_G2

0x0

Gain of the decimator in the RSSI resampling block (banked)

(7:6) FRONTEND_RESAMPLE_RSSI_G1

(7:6) FRONTEND_RESAMPLE_RSSI_G1

0x0

Gain of the interpolator in the RSSI resampling block (banked)

(5) FRONTEND_EN_RESAMPLE_RSSI

(5) FRONTEND_EN_RESAMPLE_RSSI

0x0

RSSI resampling (banked)

(4) FRONTEND_EN_RESAMPLE_PHADC

(4) FRONTEND_EN_RESAMPLE_PHADC

0x1

Phase resampling (banked)

(3:0) FRONTEND_DIV_PHADC

(3:0) FRONTEND_DIV_PHADC

0x0

Unsigned value that specifies the divider to obtain the phase ADC clock and RSSI (banked)

0x40040A5C

RF1_RX_PULSE_SHAPE

(31:28) RX_PULSE_SHAPE_RX_COEF8

(31:28) RX_PULSE_SHAPE_RX_COEF8

0xF

Rx pulse shape coefficient 8 (banked)

(27:24) RX_PULSE_SHAPE_RX_COEF7

(27:24) RX_PULSE_SHAPE_RX_COEF7

0xE

Rx pulse shape coefficient 7 (banked)

(23:20) RX_PULSE_SHAPE_RX_COEF6

(23:20) RX_PULSE_SHAPE_RX_COEF6

0xC

Rx pulse shape coefficient 6 (banked)

(19:16) RX_PULSE_SHAPE_RX_COEF5

(19:16) RX_PULSE_SHAPE_RX_COEF5

0xA

Rx pulse shape coefficient 5 (banked)

(15:12) RX_PULSE_SHAPE_RX_COEF4

(15:12) RX_PULSE_SHAPE_RX_COEF4

0x7

Rx pulse shape coefficient 4 (banked)

(11:8) RX_PULSE_SHAPE_RX_COEF3

(11:8) RX_PULSE_SHAPE_RX_COEF3

0x4

Rx pulse shape coefficient 3 (banked)

(7:4) RX_PULSE_SHAPE_RX_COEF2

(7:4) RX_PULSE_SHAPE_RX_COEF2

0x2

Rx pulse shape coefficient 2 (banked)

(3:0) RX_PULSE_SHAPE_RX_COEF1

(3:0) RX_PULSE_SHAPE_RX_COEF1

0x1

Rx pulse shape coefficient 1 (banked)

0x40040A60

RF1_REG18

(28) DELAY_LINE_CONF_MULTI_SYNC

(28) DELAY_LINE_CONF_MULTI_SYNC

0x0

Detect multiple syncs (banked)

(27:25) DELAY_LINE_CONF_DL_ISI_THR

(27:25) DELAY_LINE_CONF_DL_ISI_THR

0x1

Threshold bias for ISI compensation in the delay line sync word comparator (banked)

(22) DELAY_LINE_CONF_EN_SYNC_OK_DELAY_LINE

(22) DELAY_LINE_CONF_EN_SYNC_OK_DELAY_LINE

0x1

Use pattern_ok signal in delay line to synchronize the deserializer (banked)

(21:20) DELAY_LINE_CONF_MAX_ERR_IN_DL_SYNC

(21:20) DELAY_LINE_CONF_MAX_ERR_IN_DL_SYNC

0x0

Set the maximum errors in the delay line sync detection (banked)

(19) DELAY_LINE_CONF_EN_NOT_CAUSAL

(19) DELAY_LINE_CONF_EN_NOT_CAUSAL

0x0

Non causal processing (banked)

(18:16) DELAY_LINE_CONF_NC_SEL_OUT

(18:16) DELAY_LINE_CONF_NC_SEL_OUT

0x0

Select the output position for the non causal processing (banked)

(15:8) FSK_FCR_AMP_1_FSK_FCR_AMP1

(15:8) FSK_FCR_AMP_1_FSK_FCR_AMP1

0x1B

FSK amplitude low (banked)

(6:4) CARRIER_RECOVERY_EXTRA_FREQ_LIMIT_MAN

(6:4) CARRIER_RECOVERY_EXTRA_FREQ_LIMIT_MAN

0x5

Mantissa of the carrier recovery frequency limit (banked)

(2:0) CARRIER_RECOVERY_EXTRA_FREQ_LIMIT_EXP

(2:0) CARRIER_RECOVERY_EXTRA_FREQ_LIMIT_EXP

0x0

Exponent of the carrier recovery frequency limit (banked)

0x40040A64

RF1_REG19

(30) RSSI_BANK_EN_RSSI_DITHER

(30) RSSI_BANK_EN_RSSI_DITHER

0x0

Speed on the RSSI triangular dithering signal (banked)

(29) RSSI_BANK_FAST_RSSI

(29) RSSI_BANK_FAST_RSSI

0x0

RSSI filtering speed (banked)

(28) RSSI_BANK_EN_FAST_PRE_SYNC

(28) RSSI_BANK_EN_FAST_PRE_SYNC

0x1

Fast mode switching during the preamble reception (banked)

(27:24) RSSI_BANK_TAU_RSSI_FILTERING

(27:24) RSSI_BANK_TAU_RSSI_FILTERING

0x1

Time constant of the RSSI filtering block (banked)

(20) DECISION_USE_VIT_SOFT

(20) DECISION_USE_VIT_SOFT

0x0

Viterbi soft decoding (banked)

(19:18) DECISION_VITERBI_LEN

(19:18) DECISION_VITERBI_LEN

0x2

Set the Viterbi path length (banked)

(17) DECISION_VITERBI_POW_NLIN

(17) DECISION_VITERBI_POW_NLIN

0x1

Viterbi algorithm uses power instead of amplitude to evaluate the error on the path (banked)

(16) DECISION_EN_VITERBI_GFSK

(16) DECISION_EN_VITERBI_GFSK

0x1

Viterbi algorithm for the GFSK decoding (banked)

(15:8) FSK_FCR_AMP_3_FSK_FCR_AMP3

(15:8) FSK_FCR_AMP_3_FSK_FCR_AMP3

0x44

FSK amplitude high (banked)

(7:0) FSK_FCR_AMP_2_FSK_FCR_AMP2

(7:0) FSK_FCR_AMP_2_FSK_FCR_AMP2

0x30

FSK amplitude mid (banked)

0x40040A68

RF1_REG1A

(28:24) PA_PWR_PA_PWR

(28:24) PA_PWR_PA_PWR

0xC

Signed value that sets the PA power

(22) RSSI_BANK_ALT_USE_RSSI_ALT

(22) RSSI_BANK_ALT_USE_RSSI_ALT

0x0

Use alternative RRSI configuration (banked)

(21) RSSI_BANK_ALT_FAST_RSSI_ALT

(21) RSSI_BANK_ALT_FAST_RSSI_ALT

0x0

RSSI filtering speed (banked)

(19:16) RSSI_BANK_ALT_TAU_RSSI_FILTERING_ALT

(19:16) RSSI_BANK_ALT_TAU_RSSI_FILTERING_ALT

0x3

Time constant of the RSSI filtering block (banked)

(15:0) CORRECT_CFREQ_IF_CORRECT_CFREQ_IF

(15:0) CORRECT_CFREQ_IF_CORRECT_CFREQ_IF

0x1555

Unsigned value that specifies the IF for the Rx mode (banked)

0x40040A6C

RF1_REG1B

(31) PLL_BANK_EN_LOW_CHP_BIAS_TX

(31) PLL_BANK_EN_LOW_CHP_BIAS_TX

0x0

Set the en_low_chp_bias bit in Tx mode (banked)

(30) PLL_BANK_EN_LOW_CHP_BIAS_RX

(30) PLL_BANK_EN_LOW_CHP_BIAS_RX

0x1

Set the en_low_chp_bias bit in Rx mode (banked)

(29:28) PLL_BANK_PLL_FILTER_RES_TRIM_TX

(29:28) PLL_BANK_PLL_FILTER_RES_TRIM_TX

0x3

Modify the value of the loop filter resistor R2 when bit 5 is high in Tx mode (banked)

(27:24) PLL_BANK_IQ_PLL_0_TX

(27:24) PLL_BANK_IQ_PLL_0_TX

0x4

Charge pump bias for Tx case (banked)

(22) PLL_BANK_LOW_DR_TX

(22) PLL_BANK_LOW_DR_TX

0x0

Enable low data-rate mode in Tx mode (banked)

(21:20) PLL_BANK_PLL_FILTER_RES_TRIM_RX

(21:20) PLL_BANK_PLL_FILTER_RES_TRIM_RX

0x0

Modify the value of the loop filter resistor R2 when bit 5 is high in Rx mode (banked)

(19:16) PLL_BANK_IQ_PLL_0_RX

(19:16) PLL_BANK_IQ_PLL_0_RX

0xB

Charge pump bias for Rx (banked)

(15) ANACLK_USE_NEW_ANACK

(15) ANACLK_USE_NEW_ANACK

0x0

Use the new analog clock generator (banked)

(13:12) ANACLK_DIV_CK_RSSI

(13:12) ANACLK_DIV_CK_RSSI

0x0

Set the master clock divider for the RSSI clock (banked)

(11:10) ANACLK_DIV_CK_FILT

(11:10) ANACLK_DIV_CK_FILT

0x0

Set the master clock divider for the channel filter clock (banked)

(9:8) ANACLK_DIV_CK_PHADC

(9:8) ANACLK_DIV_CK_PHADC

0x0

Set the master clock divider for the phase ADC clock (banked)

(7:4) ANACLK_DIV_RSSI

(7:4) ANACLK_DIV_RSSI

0x1

Unsigned value that specifies the division factor for the clock controlling the RSSI (banked)

(3:0) ANACLK_DIV_FILT

(3:0) ANACLK_DIV_FILT

0x5

Unsigned value that specifies the division factor for the clock controlling the channel filter (banked)

0x40040A70

RF1_RSSI_CTRL

(31:30) RSSI_CTRL_AGC_DECAY_TAU

(31:30) RSSI_CTRL_AGC_DECAY_TAU

0x3

Time constant of the decay speed

(29) RSSI_CTRL_AGC_USE_LNA

(29) RSSI_CTRL_AGC_USE_LNA

0x1

AGC algorithm uses LNA bias

(28) RSSI_CTRL_AGC_MODE

(28) RSSI_CTRL_AGC_MODE

0x1

AGC algorithm selection

(27:26) RSSI_CTRL_AGC_WAIT

(27:26) RSSI_CTRL_AGC_WAIT

0x3

Set the wait time of the AGC after switching between state

(25) RSSI_CTRL_PAYLOAD_BLOCKS_AGC

(25) RSSI_CTRL_PAYLOAD_BLOCKS_AGC

0x1

AGC payload blocking

(24) RSSI_CTRL_BYPASS_AGC

(24) RSSI_CTRL_BYPASS_AGC

0x0

AGC algorithm bypass

(20:16) PA_PWR_OFFSET_PA_PWR_OFFSET

(20:16) PA_PWR_OFFSET_PA_PWR_OFFSET

0x0

Signed value that sets the PA power (banked)

(12:8) FILTER_BIAS_IQ_FI_BW

(12:8) FILTER_BIAS_IQ_FI_BW

0x14

Bias for the bandwidth of the channel filter (banked)

(4:0) FILTER_BIAS_IQ_FI_FC

(4:0) FILTER_BIAS_IQ_FI_FC

0xB

Bias for the central frequency of the channel filter (banked)

0x40040A74

RF1_REG1D

(31:28) AGC_PEAK_DET_PEAK_DET_TAU

(31:28) AGC_PEAK_DET_PEAK_DET_TAU

0x7

Time constant of the peak detector monostable circuit

(27:26) AGC_PEAK_DET_PEAK_DET_THR_LOW

(27:26) AGC_PEAK_DET_PEAK_DET_THR_LOW

0x0

Threshold for the low level of the peak detector

(25) AGC_PEAK_DET_PEAK_DET_THR_HIGH

(25) AGC_PEAK_DET_PEAK_DET_THR_HIGH

0x0

Threshold for the high level of the peak detector

(24) AGC_PEAK_DET_EN_AGC_PEAK

(24) AGC_PEAK_DET_EN_AGC_PEAK

0x1

Enable AGC peak detector

(23:16) AGC_THR_HIGH_AGC_THR_HIGH

(23:16) AGC_THR_HIGH_AGC_THR_HIGH

0x69

AGC threshold high level (banked)

(15:8) AGC_THR_LOW_AGC_THR_LOW

(15:8) AGC_THR_LOW_AGC_THR_LOW

0x40

AGC threshold low level (banked)

(7:4) ATT_CTRL_ATT_CTRL_MAX

(7:4) ATT_CTRL_ATT_CTRL_MAX

0xB

Maximum attenuation level in AGC algorithm

(3:0) ATT_CTRL_SET_RX_ATT_CTRL

(3:0) ATT_CTRL_SET_RX_ATT_CTRL

0x0

Attenuation level if the AGC is bypassed

0x40040A78

RF1_AGC_LUT1

(31:22) AGC_LUT_1_AGC_LEVEL_2_LO

(31:22) AGC_LUT_1_AGC_LEVEL_2_LO

0x280

AGC values level 2 (LSB)

(21:11) AGC_LUT_1_AGC_LEVEL_1

(21:11) AGC_LUT_1_AGC_LEVEL_1

0x80

AGC values level 1

(10:0) AGC_LUT_1_AGC_LEVEL_0

(10:0) AGC_LUT_1_AGC_LEVEL_0

0x0

AGC values level 0

0x40040A7C

RF1_AGC_LUT2

(31:23) AGC_LUT_2_AGC_LEVEL_5_LO

(31:23) AGC_LUT_2_AGC_LEVEL_5_LO

0x84

AGC values level 5 (LSB)

(22:12) AGC_LUT_2_AGC_LEVEL_4

(22:12) AGC_LUT_2_AGC_LEVEL_4

0x284

AGC values level 4

(11:1) AGC_LUT_2_AGC_LEVEL_3

(11:1) AGC_LUT_2_AGC_LEVEL_3

0x480

AGC values level 3

(0) AGC_LUT_2_AGC_LEVEL_2_HI

(0) AGC_LUT_2_AGC_LEVEL_2_HI

0x0

AGC values level 2 (MSB)

0x40040A80

RF1_AGC_LUT3

(31:24) AGC_LUT_3_AGC_LEVEL_8_LO

(31:24) AGC_LUT_3_AGC_LEVEL_8_LO

0x9D

AGC values level 8 (LSB)

(23:13) AGC_LUT_3_AGC_LEVEL_7

(23:13) AGC_LUT_3_AGC_LEVEL_7

0x495

AGC values level 7

(12:2) AGC_LUT_3_AGC_LEVEL_6

(12:2) AGC_LUT_3_AGC_LEVEL_6

0x485

AGC values level 6

(1:0) AGC_LUT_3_AGC_LEVEL_5_HI

(1:0) AGC_LUT_3_AGC_LEVEL_5_HI

0x2

AGC values level 5 (MSB)

0x40040A84

RF1_AGC_LUT4

(31:25) AGC_LUT_4_AGC_LEVEL_11_LO

(31:25) AGC_LUT_4_AGC_LEVEL_11_LO

0x7F

AGC values level 11 (LSB)

(24:14) AGC_LUT_4_AGC_LEVEL_10

(24:14) AGC_LUT_4_AGC_LEVEL_10

0x4FF

AGC values level 10

(13:3) AGC_LUT_4_AGC_LEVEL_9

(13:3) AGC_LUT_4_AGC_LEVEL_9

0x49F

AGC values level 9

(2:0) AGC_LUT_4_AGC_LEVEL_8_HI

(2:0) AGC_LUT_4_AGC_LEVEL_8_HI

0x4

AGC values level 8 (MSB)

0x40040A88

RF1_AGC_LUT5

(26:25) IEEE802154_OPTS_CNT_LIM_802154

(26:25) IEEE802154_OPTS_CNT_LIM_802154

0x2

Set the number of samples to wait before increasing the threshold

(24:22) IEEE802154_OPTS_CNT_OK_INC_802154

(24:22) IEEE802154_OPTS_CNT_OK_INC_802154

0x4

Set the increment to the counter that indicates that the correlators peaks are coherent

(21) IEEE802154_OPTS_USE_OS_802154

(21) IEEE802154_OPTS_USE_OS_802154

0x1

Enable the new algorithm working in the oversampled domain for the demodulation of the IEEE 802.15.4 protocol

(20) IEEE802154_OPTS_EN_DW_TEST

(20) IEEE802154_OPTS_EN_DW_TEST

0x0

Tx data-whitening before the convolutional code block

(18:16) IEEE802154_OPTS_C2B_THR

(18:16) IEEE802154_OPTS_C2B_THR

0x4

Threshold of the chip2bit correlator of the IEEE 802.15.4 protocol

(13:12) DATA_STREAMS_BER_CLK_MODE

(13:12) DATA_STREAMS_BER_CLK_MODE

0x0

Set the clock output mode for BER mode or RW mode

(10) DATA_STREAMS_RX_DATA_NOT_SAMPLED

(10) DATA_STREAMS_RX_DATA_NOT_SAMPLED

0x0

Signal rx_data in test modes sampling

(9) DATA_STREAMS_PHASE_GREY

(9) DATA_STREAMS_PHASE_GREY

0x0

Phase signal encoding

(8) DATA_STREAMS_TX_IN_CLK_TOGGLE

(8) DATA_STREAMS_TX_IN_CLK_TOGGLE

0x0

Input clock

(3:0) AGC_LUT_5_AGC_LEVEL_11_HI

(3:0) AGC_LUT_5_AGC_LEVEL_11_HI

0xE

AGC values level 11 (MSB)

0x40040A8C

RF1_AGC_ATT1

(31:30) AGC_ATT_1_AGC_ATT_AB_LO

(31:30) AGC_ATT_1_AGC_ATT_AB_LO

0x3

AGC attenuation step 10/11 (LSB)

(29:27) AGC_ATT_1_AGC_ATT_9A

(29:27) AGC_ATT_1_AGC_ATT_9A

0x5

AGC attenuation step 9/10

(26:24) AGC_ATT_1_AGC_ATT_89

(26:24) AGC_ATT_1_AGC_ATT_89

0x3

AGC attenuation step 8/9

(23:21) AGC_ATT_1_AGC_ATT_78

(23:21) AGC_ATT_1_AGC_ATT_78

0x4

AGC attenuation step 7/8

(20:18) AGC_ATT_1_AGC_ATT_67

(20:18) AGC_ATT_1_AGC_ATT_67

0x3

AGC attenuation step 6/7

(17:15) AGC_ATT_1_AGC_ATT_56

(17:15) AGC_ATT_1_AGC_ATT_56

0x2

AGC attenuation step 5/6

(14:12) AGC_ATT_1_AGC_ATT_45

(14:12) AGC_ATT_1_AGC_ATT_45

0x2

AGC attenuation step 4/5

(11:9) AGC_ATT_1_AGC_ATT_34

(11:9) AGC_ATT_1_AGC_ATT_34

0x2

AGC attenuation step 3/4

(8:6) AGC_ATT_1_AGC_ATT_23

(8:6) AGC_ATT_1_AGC_ATT_23

0x1

AGC attenuation step 2/3

(5:3) AGC_ATT_1_AGC_ATT_12

(5:3) AGC_ATT_1_AGC_ATT_12

0x1

AGC attenuation step 1/2

(2:0) AGC_ATT_1_AGC_ATT_01

(2:0) AGC_ATT_1_AGC_ATT_01

0x4

AGC attenuation step 0/1

0x40040A90

RF1_AGC_ATT2

(31:28) TIMINGS_3_T_DLL

(31:28) TIMINGS_3_T_DLL

0x2

Time needed by the DLL blocks to switch on

(27:24) TIMINGS_3_T_PLL_TX

(27:24) TIMINGS_3_T_PLL_TX

0x2

Time needed by the PLL blocks in Tx mode to switch on

(23:20) TIMINGS_2_T_SUBBAND_TX

(23:20) TIMINGS_2_T_SUBBAND_TX

0xC

Time needed by the subband algorithm to calibrate in Tx mode

(19:16) TIMINGS_2_T_TX_RF

(19:16) TIMINGS_2_T_TX_RF

0x1

Time needed by the RF blocks to switch on in Tx mode

(14:12) TIMINGS_1_T_GRANULARITY_TX

(14:12) TIMINGS_1_T_GRANULARITY_TX

0x3

Define the granularity of the timer in Tx mode

(10:8) TIMINGS_1_T_GRANULARITY_RX

(10:8) TIMINGS_1_T_GRANULARITY_RX

0x5

Define the granularity of the timer in Rx mode

(1) AGC_ATT_2_AGC_ATT_1DB

(1) AGC_ATT_2_AGC_ATT_1DB

0x0

Attenuation steps

(0) AGC_ATT_2_AGC_ATT_AB_HI

(0) AGC_ATT_2_AGC_ATT_AB_HI

0x1

AGC attenuation step 10/11 (MSB)

0x40040A94

RF1_REG25

(31) TIMEOUT_EN_RX_TIMEOUT

(31) TIMEOUT_EN_RX_TIMEOUT

0x0

Timeout of the Rx when the system is on FSM mode

(30:28) TIMEOUT_T_TIMEOUT_GR

(30:28) TIMEOUT_T_TIMEOUT_GR

0x0

Granularity of the timer in timeout Rx mode

(27:24) TIMEOUT_T_RX_TIMEOUT

(27:24) TIMEOUT_T_RX_TIMEOUT

0x0

Time that has to occur before the timeout

(21) TIMING_FAST_RX_EN_FAST_RX_TXFILT

(21) TIMING_FAST_RX_EN_FAST_RX_TXFILT

0x0

Filter Tx configuration for the fast Rx PLL

(20) TIMING_FAST_RX_EN_FAST_RX

(20) TIMING_FAST_RX_EN_FAST_RX

0x0

Fast Rx PLL

(19:16) TIMING_FAST_RX_T_RX_FAST_CHP

(19:16) TIMING_FAST_RX_T_RX_FAST_CHP

0x0

Time to switch off the fast CHP in Rx mode

(15:12) TIMINGS_5_T_RX_RF

(15:12) TIMINGS_5_T_RX_RF

0x0

Time needed by the RF blocks to switch on in Rx mode

(11:8) TIMINGS_5_T_RX_BB

(11:8) TIMINGS_5_T_RX_BB

0x1

Time needed by the BB blocks to switch on in Rx mode

(7:4) TIMINGS_4_T_SUBBAND_RX

(7:4) TIMINGS_4_T_SUBBAND_RX

0x5

Time needed by the subband algorithm to calibrate in Rx mode

(3:0) TIMINGS_4_T_PLL_RX

(3:0) TIMINGS_4_T_PLL_RX

0x1

Time needed by the PLL blocks to switch on in Rx mode

0x40040A98

RF1_BIAS_0_2

(31:28) BIAS_2_IQ_RXTX_6

(31:28) BIAS_2_IQ_RXTX_6

0x3

VCOM_MX bias

(27:24) BIAS_2_IQ_RXTX_5

(27:24) BIAS_2_IQ_RXTX_5

0x8

VCOM_LO bias

(23:20) BIAS_1_IQ_RXTX_3

(23:20) BIAS_1_IQ_RXTX_3

0x6

PrePA Casc bias

(19:16) BIAS_1_IQ_RXTX_2

(19:16) BIAS_1_IQ_RXTX_2

0x6

PrePA In bias

(15:12) BIAS_0_IQ_RXTX_1

(15:12) BIAS_0_IQ_RXTX_1

0x7

PA backoff bias

(11:8) BIAS_0_IQ_RXTX_0

(11:8) BIAS_0_IQ_RXTX_0

0x3

PA bias

(7) INTERFACE_CONF_EN_SYNC_IFACE

(7) INTERFACE_CONF_EN_SYNC_IFACE

0x0

Interfaces resynchronization

(6:4) INTERFACE_CONF_APB_WAIT_STATE

(6:4) INTERFACE_CONF_APB_WAIT_STATE

0x0

Select the number of wait states during the APB transaction

(1:0) INTERFACE_CONF_SPI_SELECT

(1:0) INTERFACE_CONF_SPI_SELECT

0x0

Select the SPI mode

0x40040A9C

RF1_BIAS_3_6

(31:28) BIAS_6_IQ_BB_0

(31:28) BIAS_6_IQ_BB_0

0x7

ACD_O bias

(27:24) BIAS_6_IQ_PLL_3

(27:24) BIAS_6_IQ_PLL_3

0x7

DLL bias

(23:20) BIAS_5_IQ_PLL_4_RX

(23:20) BIAS_5_IQ_PLL_4_RX

0x8

VCO bias for Rx mode

(19:16) BIAS_5_IQ_PLL_4_TX

(19:16) BIAS_5_IQ_PLL_4_TX

0xA

VCO bias for Tx mode

(15:12) BIAS_4_IQ_PLL_2

(15:12) BIAS_4_IQ_PLL_2

0x7

Sub-band comparator bias

(11:8) BIAS_4_IQ_PLL_1

(11:8) BIAS_4_IQ_PLL_1

0x4

Dynamic divider bias

(7:4) BIAS_3_IQ_RXTX_8

(7:4) BIAS_3_IQ_RXTX_8

0x7

IFA ctrl_c bias

(3:0) BIAS_3_IQ_RXTX_7

(3:0) BIAS_3_IQ_RXTX_7

0x7

IFA ctrl_r bias

0x40040AA0

RF1_BIAS_7_9

(31:28) BIAS_9_IQ_BB_6

(31:28) BIAS_9_IQ_BB_6

0x9

Peak detector threshold bias 0

(27:24) BIAS_9_IQ_BB_5

(27:24) BIAS_9_IQ_BB_5

0x5

Peak detector bias

(23:20) SWCAP_FSM_SB_CAP_RX

(23:20) SWCAP_FSM_SB_CAP_RX

0x0

VCO subband selection (FSM in Rx mode)

(19:16) SWCAP_FSM_SB_CAP_TX

(19:16) SWCAP_FSM_SB_CAP_TX

0x0

VCO subband selection (FSM in Tx mode)

(15:12) BIAS_8_IQ_BB_4

(15:12) BIAS_8_IQ_BB_4

0x9

RSSI_D bias

(11:8) BIAS_8_IQ_BB_3

(11:8) BIAS_8_IQ_BB_3

0xF

RSSI_G bias

(7:4) BIAS_7_IQ_BB_2

(7:4) BIAS_7_IQ_BB_2

0x6

ACD_L bias

(3:0) BIAS_7_IQ_BB_1

(3:0) BIAS_7_IQ_BB_1

0x6

ACD_C bias

0x40040AA4

RF1_BIAS_10_12

(30) SD_MASH_MASH_DITHER_TYPE

(30) SD_MASH_MASH_DITHER_TYPE

0x0

Enable the new dithering scheme

(29) SD_MASH_MASH_ENABLE

(29) SD_MASH_MASH_ENABLE

0x0

Enable the sigma delta mash

(28) SD_MASH_MASH_DITHER

(28) SD_MASH_MASH_DITHER

0x1

Enable dithering on the sigma delta mash

(27:25) SD_MASH_MASH_ORDER

(27:25) SD_MASH_MASH_ORDER

0x3

Order of the sigma delta mash

(24) SD_MASH_MASH_RSTB

(24) SD_MASH_MASH_RSTB

0x1

Reset of the sigma delta mash (active low)

(23:20) BIAS_12_LNA_AGC_BIAS_3

(23:20) BIAS_12_LNA_AGC_BIAS_3

0x6

LNA bias for AGC level 3

(19:16) BIAS_12_LNA_AGC_BIAS_2

(19:16) BIAS_12_LNA_AGC_BIAS_2

0x7

LNA bias for AGC level 2

(15:12) BIAS_11_LNA_AGC_BIAS_1

(15:12) BIAS_11_LNA_AGC_BIAS_1

0x8

LNA bias for AGC level 1

(11:8) BIAS_11_LNA_AGC_BIAS_0

(11:8) BIAS_11_LNA_AGC_BIAS_0

0x9

LNA bias for AGC level 0

(7:4) BIAS_10_IQ_BB_8

(7:4) BIAS_10_IQ_BB_8

0x0

Peak detector threshold bias 1

(3:0) BIAS_10_IQ_BB_7

(3:0) BIAS_10_IQ_BB_7

0x6

Peak detector threshold bias 2

0x40040AA8

RF1_REG2A

(27:24) SD_MASH_MASK_MASH_MASK

(27:24) SD_MASH_MASK_MASH_MASK

0x0

Mask the n LSB of the fractional part of the MASH (debug only)

(19) BIAS_EN_2_EN_PTAT

(19) BIAS_EN_2_EN_PTAT

0x1

Enable PTAT

(18:16) BIAS_EN_2_EN_BIAS_BB_HI

(18:16) BIAS_EN_2_EN_BIAS_BB_HI

0x0

Bias enable for BB (same order as biases)

(15:12) BIAS_EN_1_EN_BIAS_BB_LO

(15:12) BIAS_EN_1_EN_BIAS_BB_LO

0x0

Bias enable for BB (same order as biases)

(11:7) BIAS_EN_1_EN_BIAS_PLL

(11:7) BIAS_EN_1_EN_BIAS_PLL

0x0

Bias enable for PLL (same order as biases)

(6:0) BIAS_EN_1_EN_BIAS_RXTX

(6:0) BIAS_EN_1_EN_BIAS_RXTX

0x0

Bias enable for RxTx (same order as biases)

0x40040AAC

RF1_PLL_CTRL

(26) PLL_CTRL_DISABLE_CHP_SBS

(26) PLL_CTRL_DISABLE_CHP_SBS

0x0

Charge-pump disabling during sub-band selection (FLL and frequency ratios)

(25) PLL_CTRL_PLL_RX_48MEG

(25) PLL_CTRL_PLL_RX_48MEG

0x1

PLL frequency

(24) PLL_CTRL_SWCAP_TX_SAME_RX

(24) PLL_CTRL_SWCAP_TX_SAME_RX

0x0

Registers for Rx and Tx modes swcap in case of swcap_fsm=1

(23) PLL_CTRL_SWCAP_FSM

(23) PLL_CTRL_SWCAP_FSM

0x1

Selection of the swcap_fsm register

(22) PLL_CTRL_DLL_RSTB

(22) PLL_CTRL_DLL_RSTB

0x1

Reset signal of the DLL (active low)

(21:18) PLL_CTRL_VCO_SUBBAND_TRIM

(21:18) PLL_CTRL_VCO_SUBBAND_TRIM

0x0

VCO sub-band selection bits

(17) PLL_CTRL_SUB_SEL_OFFS_EN

(17) PLL_CTRL_SUB_SEL_OFFS_EN

0x0

Add offset to sub-band selection comparator

(16) PLL_CTRL_DIV2_CLKVCO_TEST_EN

(16) PLL_CTRL_DIV2_CLKVCO_TEST_EN

0x0

VCO signal divided by the programmable divider

(15) PLL_CTRL_VCODIV_CLK_TEST_EN

(15) PLL_CTRL_VCODIV_CLK_TEST_EN

0x0

Output on GPIO the VCO signal divided by the programmable divider

(13) PLL_CTRL_CHP_DEAD_ZONE_EN

(13) PLL_CTRL_CHP_DEAD_ZONE_EN

0x0

Charge-pump dead zone

(12:11) PLL_CTRL_CHP_CURR_OFF_TRIM_TX

(12:11) PLL_CTRL_CHP_CURR_OFF_TRIM_TX

0x3

Charge-pump offset current values selection bits in Tx mode

(10:9) PLL_CTRL_CHP_CURR_OFF_TRIM_RX

(10:9) PLL_CTRL_CHP_CURR_OFF_TRIM_RX

0x3

Charge-pump offset current values selection bits in Rx mode

(8) PLL_CTRL_HIGH_BW_FILTER_EN_TX

(8) PLL_CTRL_HIGH_BW_FILTER_EN_TX

0x1

PLL filter high bandwidth needed in Tx mode

(7) PLL_CTRL_HIGH_BW_FILTER_EN_RX

(7) PLL_CTRL_HIGH_BW_FILTER_EN_RX

0x0

PLL filter high bandwidth needed in Rx mode

(6) PLL_CTRL_FAST_CHP_EN_TX

(6) PLL_CTRL_FAST_CHP_EN_TX

0x1

High current output of the charge-pump for PLL Tx high bandwidth mode

(5) PLL_CTRL_FAST_CHP_EN_RX

(5) PLL_CTRL_FAST_CHP_EN_RX

0x0

High current output of the charge-pump for PLL Rx high bandwidth mode

(4:3) PLL_CTRL_CHP_MODE_TRIM

(4:3) PLL_CTRL_CHP_MODE_TRIM

0x0

Select the frequency inside sub-band selection

(2) PLL_CTRL_CHP_CMC_EN

(2) PLL_CTRL_CHP_CMC_EN

0x1

Common mode control block of the charge-pump

(1) PLL_CTRL_CHP_CURR_OFF_EN_TX

(1) PLL_CTRL_CHP_CURR_OFF_EN_TX

0x1

Charge-pump offset current in Tx mode

(0) PLL_CTRL_CHP_CURR_OFF_EN_RX

(0) PLL_CTRL_CHP_CURR_OFF_EN_RX

0x0

Charge-pump offset current in Rx mode

0x40040AB0

RF1_DLL_CTRL

(31:29) RSSI_TUN_1_RSSI_TUN_GAIN

(31:29) RSSI_TUN_1_RSSI_TUN_GAIN

0x1

RSSI tuning for gain

(28:24) RSSI_TUN_1_RSSI_ODD_OFFSET

(28:24) RSSI_TUN_1_RSSI_ODD_OFFSET

0x4

RSSI tuning for odd stages (offset to the even triangular wave)

(23:20) RSSI_TUN_1_RSSI_EVEN_MAX

(23:20) RSSI_TUN_1_RSSI_EVEN_MAX

0x1

RSSI tuning for even stages (maximum value of the triangular wave)

(19:16) RSSI_TUN_1_RSSI_EVEN_MIN

(19:16) RSSI_TUN_1_RSSI_EVEN_MIN

0x1

RSSI tuning for even stages (minimum value of the triangular wave)

(12) DLL_CTRL_CK_LAST_SEL_DELAY

(12) DLL_CTRL_CK_LAST_SEL_DELAY

0x0

Last SEL delay

(11) DLL_CTRL_CK_FIRST_SEL_DELAY

(11) DLL_CTRL_CK_FIRST_SEL_DELAY

0x0

First SEL delay

(10) DLL_CTRL_CK_EXT_SEL

(10) DLL_CTRL_CK_EXT_SEL

0x0

Input clock selection

(9) DLL_CTRL_CK_DIG_EN

(9) DLL_CTRL_CK_DIG_EN

0x0

Alternate ck_dig pin to output the PLL reference clock signal

(8) DLL_CTRL_CK_TEST_EN

(8) DLL_CTRL_CK_TEST_EN

0x0

Output on GPIO the PLL reference clock signal via ck_test pin

(7) DLL_CTRL_TOO_FAST_ENB

(7) DLL_CTRL_TOO_FAST_ENB

0x0

Lock range phase detector

(6) DLL_CTRL_LOCKED_DET_EN

(6) DLL_CTRL_LOCKED_DET_EN

0x1

Reference frequency multiplier locked detector

(5) DLL_CTRL_LOCKED_AUTO_CHECK_EN

(5) DLL_CTRL_LOCKED_AUTO_CHECK_EN

0x1

Frequency multiplier is out of lock (usually because some input clocks from ck_xtal or ck_ext are missing)

(4) DLL_CTRL_FAST_ENB

(4) DLL_CTRL_FAST_ENB

0x0

Disable fast mode locking of the reference frequency multiplier

(3:2) DLL_CTRL_CK_SEL_TX

(3:2) DLL_CTRL_CK_SEL_TX

0x1

Selection of the clock used as frequency reference of the PLL in Tx mode (also to ck_test and ck_dig outputs)

(1:0) DLL_CTRL_CK_SEL_RX

(1:0) DLL_CTRL_CK_SEL_RX

0x0

Selection of the clock used as frequency reference of the PLL in Rx mode (also to ck_test and ck_dig outputs)

0x40040AB4

RF1_REG2D

(29:28) PA_CONF_SW_CN

(29:28) PA_CONF_SW_CN

0x0

Harmonic 2 notch tuning

(27) PA_CONF_TX_SWITCHPA

(27) PA_CONF_TX_SWITCHPA

0x0

Switch PA

(26) PA_CONF_TX_0DBM

(26) PA_CONF_TX_0DBM

0x1

Select between PPA and PA

(25) PA_CONF_LIN_RAMP

(25) PA_CONF_LIN_RAMP

0x0

PA ramp-up linearization

(24) PA_CONF_MIN_PA_PWR

(24) PA_CONF_MIN_PA_PWR

0x1

Set the minimum power during the PA ramp-up

(23) CTRL_RX_SWITCH_LP

(23) CTRL_RX_SWITCH_LP

0x0

Switch the low-pass filter in the Rx chain

(22) CTRL_RX_USE_PEAK_DETECTOR

(22) CTRL_RX_USE_PEAK_DETECTOR

0x1

Peak detector powering

(21) CTRL_RX_START_MIX_ON_CAL

(21) CTRL_RX_START_MIX_ON_CAL

0x0

Mixer enabling

(20:16) CTRL_RX_CTRL_RX

(20:16) CTRL_RX_CTRL_RX

0xF

Rx control

(15) CTRL_ADC_PHADC_THERM_OUT_EN

(15) CTRL_ADC_PHADC_THERM_OUT_EN

0x1

Enable the buffers of phase ADC thermometric code (banked)

(14:13) CTRL_ADC_PHADC_DELLATCH

(14:13) CTRL_ADC_PHADC_DELLATCH

0x1

Phase ADC delay latch trimming (banked)

(12:8) CTRL_ADC_CTRL_ADC

(12:8) CTRL_ADC_CTRL_ADC

0x5

Phase ADC control (banked)

(6:5) RSSI_TUN_2_RSSI_TRI_CK_DIV

(6:5) RSSI_TUN_2_RSSI_TRI_CK_DIV

0x0

Speed on the RSSI triangular dithering signal (cf reg RSSI_TUN)

(4) RSSI_TUN_2_RSSI_ONE_CK_RSSI_PHADC

(4) RSSI_TUN_2_RSSI_ONE_CK_RSSI_PHADC

0x0

RSSI and phase ADC clocks sharing

(3) RSSI_TUN_2_RSSI_FULL

(3) RSSI_TUN_2_RSSI_FULL

0x1

RSSI full scale

(2) RSSI_TUN_2_RSSI_1DB

(2) RSSI_TUN_2_RSSI_1DB

0x0

LSB resolution

(1:0) RSSI_TUN_2_RSSI_PRE_ATT

(1:0) RSSI_TUN_2_RSSI_PRE_ATT

0x3

Pre attenuation of the RSSI signal

0x40040AB8

RF1_REG2E

(31:24) XTAL_TRIM_XTAL_TRIM_INIT

(31:24) XTAL_TRIM_XTAL_TRIM_INIT

0x60

Initial trimming of the XTAL

(23:16) XTAL_TRIM_XTAL_TRIM

(23:16) XTAL_TRIM_XTAL_TRIM

0x60

Trimming of the XTAL

(12) ENABLES_SEPARATE_PPA_CASC

(12) ENABLES_SEPARATE_PPA_CASC

0x0

PA cascode bit

(11:6) ENABLES_EN_RXTX

(11:6) ENABLES_EN_RXTX

0x0

Enable signals

(5:0) ENABLES_EN_BB

(5:0) ENABLES_EN_BB

0x0

Enable signals for the BB

0x40040ABC

RF1_XTAL_CTRL

(31:28) XTAL_CTRL_XO_THR_HIGH

(31:28) XTAL_CTRL_XO_THR_HIGH

0xC

High threshold for XTAL trimming

(27:24) XTAL_CTRL_XO_THR_LOW

(27:24) XTAL_CTRL_XO_THR_LOW

0x3

Low threshold for XTAL trimming

(23:22) XTAL_CTRL_XO_A_S_CURR_SEL_HIGH

(23:22) XTAL_CTRL_XO_A_S_CURR_SEL_HIGH

0x2

Value of after_startup_curr_sel when level is higher than xo_thr_high

(21:20) XTAL_CTRL_XO_A_S_CURR_SEL_LOW

(21:20) XTAL_CTRL_XO_A_S_CURR_SEL_LOW

0x0

Value of after_startup_curr_sel when level is lower than xo_thr_low

(19) XTAL_CTRL_LOW_CLK_READY_TH_EN

(19) XTAL_CTRL_LOW_CLK_READY_TH_EN

0x0

clk_ready threshold

(18) XTAL_CTRL_XTAL_CTRL_BYPASS

(18) XTAL_CTRL_XTAL_CTRL_BYPASS

0x0

Bypass the XTAL control algorithm

(17) XTAL_CTRL_DIG_CLK_IN_SEL

(17) XTAL_CTRL_DIG_CLK_IN_SEL

0x0

Clock selection for the digital block

(16) XTAL_CTRL_XO_EN_B_REG

(16) XTAL_CTRL_XO_EN_B_REG

0x1

XTAL oscillator enable

(15:14) XTAL_CTRL_XTAL_CKDIV

(15:14) XTAL_CTRL_XTAL_CKDIV

0x0

XTAL trimming speed

(13) XTAL_CTRL_CLK_OUT_EN_B

(13) XTAL_CTRL_CLK_OUT_EN_B

0x0

Output clock to go to main IP

(12) XTAL_CTRL_REG_VALUE_SEL

(12) XTAL_CTRL_REG_VALUE_SEL

0x0

Control bits of xtal_reg

(11:10) XTAL_CTRL_AFTERSTARTUP_CURR_SEL

(11:10) XTAL_CTRL_AFTERSTARTUP_CURR_SEL

0x1

Selection of the current before amplitude stabilization but after starting-up in active transistors of the core oscillator

(9:8) XTAL_CTRL_STARTUP_CURR_SEL

(9:8) XTAL_CTRL_STARTUP_CURR_SEL

0x1

Selection of the starting-up current in active transistors of the core oscillator

(7) XTAL_CTRL_INV_CLK_DIG

(7) XTAL_CTRL_INV_CLK_DIG

0x0

Invert clock on clk_dig output

(6) XTAL_CTRL_INV_CLK_PLL

(6) XTAL_CTRL_INV_CLK_PLL

0x0

Invert clock on clk_pll output

(5) XTAL_CTRL_FORCE_CLK_READY

(5) XTAL_CTRL_FORCE_CLK_READY

0x0

Force output clocks on clk_pll, clk_dig and clk_out

(4) XTAL_CTRL_CLK_DIG_EN_B

(4) XTAL_CTRL_CLK_DIG_EN_B

0x0

Disable the output clock to go to digital (clk_dig output stay low)

(3) XTAL_CTRL_BUFF_EN_B

(3) XTAL_CTRL_BUFF_EN_B

0x0

XTAL buffer disabling

(2) XTAL_CTRL_HP_MODE

(2) XTAL_CTRL_HP_MODE

0x0

Bias current increase in the clock buffer

(1) XTAL_CTRL_LP_MODE

(1) XTAL_CTRL_LP_MODE

0x0

Bias current decrease in the clock buffer

(0) XTAL_CTRL_EXT_CLK_MODE

(0) XTAL_CTRL_EXT_CLK_MODE

0x0

Use XTAL pads as external clock input

0x40040AC0

RF1_SUBBAND

(31:24) SUBBAND_OFFSET_SB_OFFSET_RX

(31:24) SUBBAND_OFFSET_SB_OFFSET_RX

0xF1

Offset to add in frequency count in order to compensate the offset of the varicap

(23:16) SUBBAND_OFFSET_SB_OFFSET

(23:16) SUBBAND_OFFSET_SB_OFFSET

0xD0

Offset to add in frequency count in order to compensate the offset of the varicap

(15:12) SWCAP_LIM_SB_MAX_VAL

(15:12) SWCAP_LIM_SB_MAX_VAL

0xF

Maximum subband value in linear search subband (freq and comp)

(11:8) SWCAP_LIM_SB_MIN_VAL

(11:8) SWCAP_LIM_SB_MIN_VAL

0x0

Minimum subband value in linear search subband (freq and comp)

(7) SUBBAND_CONF_SB_FLL_MODE

(7) SUBBAND_CONF_SB_FLL_MODE

0x1

FLL mode for the subband selection

(6) SUBBAND_CONF_SB_INV_BAND

(6) SUBBAND_CONF_SB_INV_BAND

0x0

Invert the meaning of sb_high and sb_low

(5:4) SUBBAND_CONF_SB_FREQ_CNT

(5:4) SUBBAND_CONF_SB_FREQ_CNT

0x0

The length to count in frequency mode

(3:2) SUBBAND_CONF_SB_WAIT_T

(3:2) SUBBAND_CONF_SB_WAIT_T

0x0

Time to wait to the PLL to settle

(1:0) SUBBAND_CONF_SB_MODE

(1:0) SUBBAND_CONF_SB_MODE

0x0

Sub-band algorithm mode

0x40040AC4

RF1_REG31

(31:30) RSSI_DETECT_RSSI_DET_CR_LEN

(31:30) RSSI_DETECT_RSSI_DET_CR_LEN

0x0

Number of samples to estimate the carrier offset (banked)

(29:28) RSSI_DETECT_RSSI_DET_WAIT

(29:28) RSSI_DETECT_RSSI_DET_WAIT

0x0

Symbols to wait after the RSSI detection (banked)

(27:26) RSSI_DETECT_RSSI_DET_DIFF_LL

(27:26) RSSI_DETECT_RSSI_DET_DIFF_LL

0x0

Set the distance between the actual value and the subtracted one (banked)

(25) RSSI_DETECT_EN_ABS_RSSI_DETECT

(25) RSSI_DETECT_EN_ABS_RSSI_DETECT

0x0

Absolute RSSI detection (banked)

(24) RSSI_DETECT_EN_DIFF_RSSI_DETECT

(24) RSSI_DETECT_EN_DIFF_RSSI_DETECT

0x0

Differential RSSI detection (banked)

(23) SUBBAND_CORR_SUBBAND_CORR_EN

(23) SUBBAND_CORR_SUBBAND_CORR_EN

0x0

Subband correction

(22:20) SUBBAND_CORR_SUBBAND_CORR_RX

(22:20) SUBBAND_CORR_SUBBAND_CORR_RX

0x0

Subband correction in Rx

(18:16) SUBBAND_CORR_SUBBAND_CORR_TX

(18:16) SUBBAND_CORR_SUBBAND_CORR_TX

0x0

Subband correction in Tx

(11) TXRX_CONF_INV_CLK_PLL_TX

(11) TXRX_CONF_INV_CLK_PLL_TX

0x0

Invert PLL clock when the radio is in Tx mode

(10) TXRX_CONF_INV_CLK_DIG_TX

(10) TXRX_CONF_INV_CLK_DIG_TX

0x0

Invert digital clock when the radio is in Tx mode

(9:8) TXRX_CONF_SB_WAIT_T_TX

(9:8) TXRX_CONF_SB_WAIT_T_TX

0x0

Xor value to apply to sb_wait_t (register SUBBAND_CONF) when the radio is in Tx mode

(7) PA_RAMPUP_FULL_PA_RAMPUP

(7) PA_RAMPUP_FULL_PA_RAMPUP

0x1

PA rampup configuration

(6:4) PA_RAMPUP_DEL_PA_RAMPUP

(6:4) PA_RAMPUP_DEL_PA_RAMPUP

0x4

Time to wait to start the ramp-up after the PA enable is detected

(3:2) PA_RAMPUP_TAU_PA_RAMPUP

(3:2) PA_RAMPUP_TAU_PA_RAMPUP

0x0

Time constant of the ramp-up/ramp-down

(1) PA_RAMPUP_EN_PA_RAMPDOWN

(1) PA_RAMPUP_EN_PA_RAMPDOWN

0x1

PA ramp-down

(0) PA_RAMPUP_EN_PA_RAMPUP

(0) PA_RAMPUP_EN_PA_RAMPUP

0x1

PA ramp-up linearization

0x40040AC8

RF1_DEMOD_CTRL

(31) SYNC_WORD_CORR_EN_SYNC_WORD_CORR

(31) SYNC_WORD_CORR_EN_SYNC_WORD_CORR

0x1

Sync word bias correction with RSSI detection (banked)

(29:24) SYNC_WORD_CORR_SYNC_WORD_BIAS

(29:24) SYNC_WORD_CORR_SYNC_WORD_BIAS

0x8

Set the sync word bias (banked)

(23:16) RSSI_DETECT_ABS_THR_RSSI_DET_ABS_THR

(23:16) RSSI_DETECT_ABS_THR_RSSI_DET_ABS_THR

0x0

Threshold used for absolute RSSI detection

(15:8) RSSI_DETECT_DIFF_THR_RSSI_DET_DIFF_THR

(15:8) RSSI_DETECT_DIFF_THR_RSSI_DET_DIFF_THR

0x0

Threshold used for differential RSSI detection

(7) DEMOD_CTRL_DL_SYNC_NO_DATA

(7) DEMOD_CTRL_DL_SYNC_NO_DATA

0x1

No data going through the demodulator, until the delay line detects the sync word (banked)

(6) DEMOD_CTRL_EN_DELLINE_SYNC_DET

(6) DEMOD_CTRL_EN_DELLINE_SYNC_DET

0x1

Sync word detection in the delay line (banked)

(5) DEMOD_CTRL_RSSI_DET_FILT

(5) DEMOD_CTRL_RSSI_DET_FILT

0x0

Additional filtering on the RSSI value (banked)

(4) DEMOD_CTRL_EN_FAST_CLK_RECOV

(4) DEMOD_CTRL_EN_FAST_CLK_RECOV

0x0

Clock recovery during the resto of the preamble (banked)

(3) DEMOD_CTRL_EN_MIN_MAX_MF

(3) DEMOD_CTRL_EN_MIN_MAX_MF

0x0

Min max algo after the matched filter (banked)

(2) DEMOD_CTRL_EN_PRE_SYNC

(2) DEMOD_CTRL_EN_PRE_SYNC

0x0

Sync detection on the non-delayed path (banked)

(1) DEMOD_CTRL_BLOCK_RSSI_DET

(1) DEMOD_CTRL_BLOCK_RSSI_DET

0x0

RSSI detection during the slow-down period (banked)

(0) DEMOD_CTRL_EARLY_FINE_RECOV

(0) DEMOD_CTRL_EARLY_FINE_RECOV

0x0

Early fine recovery after the packet detection or pre-sync (banked)

0x40040ACC

RF1_REG33

(26:24) CK_DIV_1_6_CK_DIV_1_6

(26:24) CK_DIV_1_6_CK_DIV_1_6

0x0

Clock division factor for ck_div_1_6

(23:16) SPARES_SPARES

(23:16) SPARES_SPARES

0x0

Spare bits

(14) PADS_PE_DS_GPIO_DS

(14) PADS_PE_DS_GPIO_DS

0x0

Increased drive strength of the digital pads

(13) PADS_PE_DS_GPIO_PE

(13) PADS_PE_DS_GPIO_PE

0x0

Pull-up of the GPIO pads

(12) PADS_PE_DS_NRESET_PE

(12) PADS_PE_DS_NRESET_PE

0x0

Pull-up of the NRESET pads

(11) PADS_PE_DS_SPI_MISO_PE

(11) PADS_PE_DS_SPI_MISO_PE

0x0

Pull-up of the SPI MISO pads

(10) PADS_PE_DS_SPI_MOSI_PE

(10) PADS_PE_DS_SPI_MOSI_PE

0x0

Pull-up of the SPI MOSI pads

(9) PADS_PE_DS_SPI_SCLK_PE

(9) PADS_PE_DS_SPI_SCLK_PE

0x0

Pull-up of the SPI CLK pads

(8) PADS_PE_DS_SPI_CS_N_PE

(8) PADS_PE_DS_SPI_CS_N_PE

0x0

Pull-up of the SPI CSN pads

(7:6) SUBBAND_FLL_SB_FLL_DITHER

(7:6) SUBBAND_FLL_SB_FLL_DITHER

0x0

Select the dithering

(5:4) SUBBAND_FLL_SB_FLL_CIC_TAU

(5:4) SUBBAND_FLL_SB_FLL_CIC_TAU

0x3

Set the CIC decimator factor

(3) SUBBAND_FLL_SB_FLL_PH_4_N8

(3) SUBBAND_FLL_SB_FLL_PH_4_N8

0x0

Phases in the frequency detector

(2:0) SUBBAND_FLL_SB_FLL_WAIT

(2:0) SUBBAND_FLL_SB_FLL_WAIT

0x3

Set the number of CIC samples before stopping the FLL

0x40040AD0

RF1_REG34

(29:24) CLK_RECOVERY_CLK_RECOV_CORR

(29:24) CLK_RECOVERY_CLK_RECOV_CORR

0x4

Number of samples that covers the clock recovery correlator

(23:16) CLK_RECOVERY_CLK_AB_LIMIT

(23:16) CLK_RECOVERY_CLK_AB_LIMIT

0x80

Time constant for switch the clock phase if chosen wrong in clk recovery algorithm

(15) TX_PRE_DIST_EN_PRE_DIST

(15) TX_PRE_DIST_EN_PRE_DIST

0x1

Tx pre-distortion filter (banked)

(13:8) TX_PRE_DIST_PRE_DIST_B0

(13:8) TX_PRE_DIST_PRE_DIST_B0

0x2E

Coefficient b0 of the Tx pre-distortion filter (banked)

(5:0) TX_PRE_DIST_PRE_DIST_A0

(5:0) TX_PRE_DIST_PRE_DIST_A0

0x2F

Coefficient a0 of the Tx pre-distortion filter (banked)

0x40040AD4

RF1_BLE_LR

(30:24) BLR_SYNC_THRESHOLD_BLE_SYNC_THR

(30:24) BLR_SYNC_THRESHOLD_BLE_SYNC_THR

0x38

Threshold for the BLR sync word detector

(19:16) BLR_PREAMBLE_BLE_PRE_THR

(19:16) BLR_PREAMBLE_BLE_PRE_THR

0x1

Threshold for the BLR preamble detector

(15) BLE_LONG_RANGE_BLR_PUT_RI_FIFO

(15) BLE_LONG_RANGE_BLR_PUT_RI_FIFO

0x1

During the reception the RI (rate indicator) is put into the Rx FIFO (banked)

(14) BLE_LONG_RANGE_BLR500_NO_ROUGH

(14) BLE_LONG_RANGE_BLR500_NO_ROUGH

0x1

Rough recovery is stopped during the 500kbps payloads of BLR packets (banked)

(13) BLE_LONG_RANGE_BLR_LIN_FILTER

(13) BLE_LONG_RANGE_BLR_LIN_FILTER

0x1

Matched filter (banked)

(12) BLE_LONG_RANGE_EN_BLR_FLUSH

(12) BLE_LONG_RANGE_EN_BLR_FLUSH

0x1

Viterbi path 0 flushing at the end of the packet (banked)

(11) BLE_LONG_RANGE_BLR_USE_EXT_LEN

(11) BLE_LONG_RANGE_BLR_USE_EXT_LEN

0x0

BLR_PKT_LEN for flushing out the Viterbi (banked)

(10) BLE_LONG_RANGE_DISABLE_BLR_TX

(10) BLE_LONG_RANGE_DISABLE_BLR_TX

0x0

Long Range feature in Tx mode (banked)

(9) BLE_LONG_RANGE_BLR_500_N125

(9) BLE_LONG_RANGE_BLR_500_N125

0x0

Data rate selection (banked)

(8) BLE_LONG_RANGE_EN_BLR

(8) BLE_LONG_RANGE_EN_BLR

0x0

BLE long range mode (banked)

(4) HW_TRIGGER_HW_TRIG_GPIO

(4) HW_TRIGGER_HW_TRIG_GPIO

0x0

HW trigger is mapped on the GPIO instead of the Tx_on signal 0x0

(3) HW_TRIGGER_HW_TRIG_SUBBAND

(3) HW_TRIGGER_HW_TRIG_SUBBAND

0x0

Activate the sub-band selection during the Tx activation

(2) HW_TRIGGER_HW_TRIG_TX_NRX

(2) HW_TRIGGER_HW_TRIG_TX_NRX

0x0

Activate the Tx mode

(1) HW_TRIGGER_HW_TRIG_LOW

(1) HW_TRIGGER_HW_TRIG_LOW

0x0

Set the trigger polarity

(0) HW_TRIGGER_HW_TRIG_ACTIVE

(0) HW_TRIGGER_HW_TRIG_ACTIVE

0x0

Enable HW trigger

0x40040AD8

RF1_REG36

(30:28) IQ_SPARES_EN_BIAS_SPARE

(30:28) IQ_SPARES_EN_BIAS_SPARE

0x0

Enable for IQ spares

(27:24) IQ_SPARES_IQ_SPARE_2

(27:24) IQ_SPARES_IQ_SPARE_2

0x0

Spare bias 2

(23:20) IQ_SPARES_IQ_SPARE_1

(23:20) IQ_SPARES_IQ_SPARE_1

0x0

Spare bias 1

(19:16) IQ_SPARES_IQ_SPARE_0

(19:16) IQ_SPARES_IQ_SPARE_0

0x0

Spare bias 0

(8) MISC_ISO_VDDA

(8) MISC_ISO_VDDA

0x0

Isolate VDDA signals

(5) BLR_DEMAPPER_BLR_SEND_DECODED_RI

(5) BLR_DEMAPPER_BLR_SEND_DECODED_RI

0x0

Fully decode the rate indicator

(4) BLR_DEMAPPER_BLR_USE_EXT_VIT_GFSK

(4) BLR_DEMAPPER_BLR_USE_EXT_VIT_GFSK

0x1

500kbps BLR uses the Viterbi GFSK decision

(3:2) BLR_DEMAPPER_BLR_500_DPHASE

(3:2) BLR_DEMAPPER_BLR_500_DPHASE

0x3

Set the distance between samples for the phase to frequency conversion in S2 mode

(1) BLR_DEMAPPER_BLR_500_LOW_GAIN

(1) BLR_DEMAPPER_BLR_500_LOW_GAIN

0x0

Set the low gain in S2 mode

(0) BLR_DEMAPPER_BLR_125_LOW_GAIN

(0) BLR_DEMAPPER_BLR_125_LOW_GAIN

0x0

Set the low gain in S8 mode

0x40040ADC

RF1_PROT_TIMER

(31) PROT_TIMER_CONF_EN_PROT_TIMER

(31) PROT_TIMER_CONF_EN_PROT_TIMER

0x0

Enable the protocol timer

(29:27) PROT_TIMER_CONF_PT_T_STP_1

(29:27) PROT_TIMER_CONF_PT_T_STP_1

0x0

Configure the time stamp 1

(26:24) PROT_TIMER_CONF_PT_T_STP_0

(26:24) PROT_TIMER_CONF_PT_T_STP_0

0x0

Configure the time stamp 0

(22) STAGING_PS_NZ_START_BIT

(22) STAGING_PS_NZ_START_BIT

0x0

Select the frequency offset

(21) STAGING_PS_NZ_START

(21) STAGING_PS_NZ_START

0x0

Start the pulse shaper with a +/- 250 kHz frequency offset

(20) STAGING_DEL_PA_RAMPDW

(20) STAGING_DEL_PA_RAMPDW

0x0

Delay the PA ramp-down by 4.5 us

(19) STAGING_PEAK_DET_TH_SHIFT

(19) STAGING_PEAK_DET_TH_SHIFT

0x0

Peak detector threshold shift

(18:17) STAGING_AGC_DERIV_LVL

(18:17) STAGING_AGC_DERIV_LVL

0x2

Select the AGC derivative level

(16) STAGING_AGC_USE_DERIV

(16) STAGING_AGC_USE_DERIV

0x0

AGC algorithm uses the derivative information to accelerate the AGC settling

(15:8) BLE_DTM_BLE_DTM_LEN

(15:8) BLE_DTM_BLE_DTM_LEN

0x25

Set the BLE DTM packet length

(7) BLE_DTM_EN_BLE_DTM

(7) BLE_DTM_EN_BLE_DTM

0x0

Enable the BLE DTM automatic packets

(3:0) BLE_DTM_BLE_DTM_PKT_TYPE

(3:0) BLE_DTM_BLE_DTM_PKT_TYPE

0x0

Set the BLE DTM packet type (see Bluetooth specification)

0x40040AE0

RF1_CTE_OPTS

(29) CTE_OPTS_RECT_PS_CTE

(29) CTE_OPTS_RECT_PS_CTE

0x0

Use rectangular pulse shape during the CTE

(28) CTE_OPTS_USE_CTE_WO_CP

(28) CTE_OPTS_USE_CTE_WO_CP

0x0

Enable the CTE without reading or inserting the CP

(27) CTE_OPTS_CTE_AMPL

(27) CTE_OPTS_CTE_AMPL

0x0

Enable the usage of the RSSI values to adapt the amplitude of the IQ signal based to the RSSI value

(26) CTE_OPTS_DF_AOA_SLOT_TIME

(26) CTE_OPTS_DF_AOA_SLOT_TIME

0x0

Indicate the switching/sampling slot period for AoA

(25) CTE_OPTS_CP_INSERT

(25) CTE_OPTS_CP_INSERT

0x0

Force the CP bit in the packet header to 1

(24) CTE_OPTS_EN_READ_CP

(24) CTE_OPTS_EN_READ_CP

0x0

CP bit is read in the packet header (BLE standard)

(23:16) CTE_OPTS_CTE_INFO

(23:16) CTE_OPTS_CTE_INFO

0x0

Set the CTEInfo field in the packet header while cp_insert is set to 1

(14:10) ASK_MOD_ASK_MAX

(14:10) ASK_MOD_ASK_MAX

0xC

Set the maximum value for the ASK modulation

(9:5) ASK_MOD_ASK_MIN

(9:5) ASK_MOD_ASK_MIN

0x0

Set the minimum value for the ASK modulation

(4:1) ASK_MOD_ASK_CNT

(4:1) ASK_MOD_ASK_CNT

0x7

Set the how long to count for the ASK modulation

(0) ASK_MOD_EN_RSSI_ASK

(0) ASK_MOD_EN_RSSI_ASK

0x0

PA will perform an ASK modulation

0x40040AE4

RF1_PT_DELTA_0

(31:30) PT_DELTA_TS_0_PT_DELTA_T0_MULT

(31:30) PT_DELTA_TS_0_PT_DELTA_T0_MULT

0x0

Multiplier for the delta t0

(19:0) PT_DELTA_TS_0_PT_DELTA_T0

(19:0) PT_DELTA_TS_0_PT_DELTA_T0

0x0

Delta t0 for the protocol timer

0x40040AE8

RF1_PT_DELTA_1

(31:30) PT_DELTA_TS_1_PT_DELTA_T1_MULT

(31:30) PT_DELTA_TS_1_PT_DELTA_T1_MULT

0x0

Multiplier for the delta t1

(19:0) PT_DELTA_TS_1_PT_DELTA_T1

(19:0) PT_DELTA_TS_1_PT_DELTA_T1

0x0

Delta t1 for the protocol timer

0x40040AEC

RF1_CTE_IF

(25:16) CTE_CTRL_DELAY_TX_DF_DELAY_TX

(25:16) CTE_CTRL_DELAY_TX_DF_DELAY_TX

0x0

Delay (in 62.5ns) form the serializer up to the antenna in direction finding (banked)

(15) ANTENNA_CONF_DF_IND_PATTERN

(15) ANTENNA_CONF_DF_IND_PATTERN

0x0

Separate the antenna switching pattern from the reference one

(14) ANTENNA_CONF_DF_IND_ANTENNA

(14) ANTENNA_CONF_DF_IND_ANTENNA

0x0

Make the antenna for DF independent from the rest of the packet

(13:8) ANTENNA_CONF_ANT_LUT_M

(13:8) ANTENNA_CONF_ANT_LUT_M

0x0

Number of states used (-1) in the antenna LUT

(5) CTE_AUTO_PULL_EXT_IQ_SMP_TYPE

(5) CTE_AUTO_PULL_EXT_IQ_SMP_TYPE

0x0

Select the external IQ sample signal qualifier type

(4) CTE_AUTO_PULL_IQ_MSB

(4) CTE_AUTO_PULL_IQ_MSB

0x0

Select which signal is sent over the MSB in case of a 16bits buffers

(3:2) CTE_AUTO_PULL_IQ_DATA_BUS_SIZE

(3:2) CTE_AUTO_PULL_IQ_DATA_BUS_SIZE

0x0

Select the bus data size of IQ signals

(1) CTE_AUTO_PULL_CTE_QUAL

(1) CTE_AUTO_PULL_CTE_QUAL

0x0

Select the CTE data qualifier

(0) CTE_AUTO_PULL_EN_CTE_AUTO_PULL

(0) CTE_AUTO_PULL_EN_CTE_AUTO_PULL

0x0

Enable the automatic push of CTE data to an external IP

0x40040AF0

RF1_CTE_CTRL

(25:16) CTE_CTRL_DELAY_RX_DF_DELAY_SWITCH_RX

(25:16) CTE_CTRL_DELAY_RX_DF_DELAY_SWITCH_RX

0x0

Delay (in 62.5ns) from the antenna up to the deserializer in direction finding (banked)

(9:0) CTE_CTRL_DELAY_RX_DF_DELAY_SAMPLE_RX

(9:0) CTE_CTRL_DELAY_RX_DF_DELAY_SAMPLE_RX

0x0

Delay (in 62.5ns) from the matched filter up to the deserializer in direction finding (banked)

0x40040AF4

RF1_AGC_ADVANCED

(26:16) AGC_SWITCHES_AGC_SHORTS_LUT

(26:16) AGC_SWITCHES_AGC_SHORTS_LUT

0x0

Array of values that indicates if the highpass shorts must be set for the AGC state passage from n -> n+1

(8) DEBUG_FAKE_IQ_SAMPLES

(8) DEBUG_FAKE_IQ_SAMPLES

0x0

Generate fake IQ samples

(7:4) AGC_ADVANCED_AGC_TAU_SHORTS

(7:4) AGC_ADVANCED_AGC_TAU_SHORTS

0x0

Time constant that indicates the time that shorts must be on

(3) AGC_ADVANCED_AGC_EN_SHORT_PHADC

(3) AGC_ADVANCED_AGC_EN_SHORT_PHADC

0x0

Enable the short on the phase ADC highpass filter

(2) AGC_ADVANCED_AGC_EN_SHORT_IFA

(2) AGC_ADVANCED_AGC_EN_SHORT_IFA

0x0

Enable the short on the IFA highpass filter

(1) AGC_ADVANCED_AGC_USE_SHORTS

(1) AGC_ADVANCED_AGC_USE_SHORTS

0x0

Enable the usage of the shorts located in the BB path

(0) AGC_ADVANCED_AGC_FULL_SPEED

(0) AGC_ADVANCED_AGC_FULL_SPEED

0x0

Enable the maximum speed in AGC

0x40040AF8

RF1_DATA_STREAMING

(9) DATA_STREAMING_DMA_PHASE_TYPE

(9) DATA_STREAMING_DMA_PHASE_TYPE

0x0

Use the phase after the rescaler instead of the raw phase from phase ADC (banked)

(8) DATA_STREAMING_DMA_EN_BUS

(8) DATA_STREAMING_DMA_EN_BUS

0x0

Enable the DMA bus on the IP interface (banked)

(6) DATA_STREAMING_PERIODIC_SAMPLE_AFTER_CTE

(6) DATA_STREAMING_PERIODIC_SAMPLE_AFTER_CTE

0x1

Restart sampling after the CTE period (banked)

(5) DATA_STREAMING_PERIODIC_SAMPLE_AT_SYNC

(5) DATA_STREAMING_PERIODIC_SAMPLE_AT_SYNC

0x0

Start sampling at the sync detection signal from the delay line (banked)

(4) DATA_STREAMING_PERIODIC_SAMPLE_OSR_CLK

(4) DATA_STREAMING_PERIODIC_SAMPLE_OSR_CLK

0x0

Oversample (8x) the reference clock of the periodic sample (banked)

(3:1) DATA_STREAMING_PERIODIC_SAMPLE_OSR

(3:1) DATA_STREAMING_PERIODIC_SAMPLE_OSR

0x3

Division factor (-1) of for the sampling period of the periodic IQ sampling (banked)

(0) DATA_STREAMING_PERIODIC_SAMPLE_EN_IQ

(0) DATA_STREAMING_PERIODIC_SAMPLE_EN_IQ

0x0

Sample periodically I and Q channels after the matched filter and put into the IQ FIFO (banked)

0x40040AFC

RF1_REVISION

-

(31:24) CHIP_ID

0x30

Remapped register of CHIP_ID

0x40040B00

RF1_FSM_CTRL

-

(31:30) RXFIFO_STATUS_RX_BIST_ERRORS

0x0

Rx FIFO BIST result

(31:25) RXFIFO_STATUS_RX_BIST

-

N/A

Start the bist test on the Rx FIFO (code 0x5d)

-

(29) RXFIFO_STATUS_RX_NEAR_UNDERFLOW

0x0

Rx FIFO near underflow

-

(28) RXFIFO_STATUS_RX_NEAR_OVERFLOW

0x0

Rx FIFO near overflow

-

(27) RXFIFO_STATUS_RX_UNDERFLOW

0x0

Rx FIFO underflow

-

(26) RXFIFO_STATUS_RX_OVERFLOW

0x0

Rx FIFO overflow

-

(25) RXFIFO_STATUS_RX_FULL

0x0

Rx FIFO full

-

(24) RXFIFO_STATUS_RX_EMPTY

0x0

Rx FIFO empty

(24) RXFIFO_STATUS_RX_FLUSH

-

N/A

Rx FIFO flush

-

(23:22) TXFIFO_STATUS_TX_BIST_ERRORS

0x0

Tx FIFO BIST result

(23:17) TXFIFO_STATUS_TX_BIST

-

N/A

Start the bist test on the Tx FIFO (code 0x5d)

-

(21) TXFIFO_STATUS_TX_NEAR_UNDERFLOW

0x0

Tx FIFO near underflow

-

(20) TXFIFO_STATUS_TX_NEAR_OVERFLOW

0x0

Tx FIFO near overflow

-

(19) TXFIFO_STATUS_TX_UNDERFLOW

0x0

Tx FIFO underflow

-

(18) TXFIFO_STATUS_TX_OVERFLOW

0x0

Tx FIFO overflow

-

(17) TXFIFO_STATUS_TX_FULL

0x0

Tx FIFO full

-

(16) TXFIFO_STATUS_TX_EMPTY

0x0

Tx FIFO empty

(16) TXFIFO_STATUS_TX_FLUSH

-

N/A

Tx FIFO flush

-

(10) FSM_STATUS_TX_NRX

0x0

Select Rx or Tx mode

-

(9:8) FSM_STATUS_STATUS

0x0

Status of the FSM

(3) FSM_MODE_RESET

-

N/A

FSM reset

-

(2) FSM_MODE_RX_MODE

0x0

Rx status

(2) FSM_MODE_TX_NRX

-

N/A

Set the radio in Tx or Rx mode

-

(1) FSM_MODE_TX_MODE

0x0

Tx status

(1:0) FSM_MODE_MODE

-

N/A

Set the FSM mode

-

(0) FSM_MODE_N_IDLE

0x0

FSM status

0x40040B04

RF1_IQFIFO_STATUS

-

(24:16) TXFIFO_COUNT_TX_COUNT

0x0

Number of bytes in the Tx FIFO

-

(15:8) IQFIFO_COUNT_IQ_COUNT

0x0

Number of bytes in the IQ FIFO

-

(7:6) IQFIFO_STATUS_IQ_BIST_ERRORS

0x0

IQ FIFO BIST result

(7:1) IQFIFO_STATUS_IQ_BIST

-

N/A

Start the BIST test on the IQ FIFO (code 0x5d)

-

(5) IQFIFO_STATUS_IQ_NEAR_UNDERFLOW

0x0

IQ FIFO near underflow

-

(4) IQFIFO_STATUS_IQ_NEAR_OVERFLOW

0x0

IQ FIFO near overflow

-

(3) IQFIFO_STATUS_IQ_UNDERFLOW

0x0

IQ FIFO underflow

-

(2) IQFIFO_STATUS_IQ_OVERFLOW

0x0

IQ FIFO overflow

-

(1) IQFIFO_STATUS_IQ_FULL

0x0

IQ FIFO full

-

(0) IQFIFO_STATUS_IQ_EMPTY

0x0

IQ FIFO empty

(0) IQFIFO_STATUS_FLUSH

-

N/A

IQ FIFO flush

0x40040B08

RF1_TXFIFO

(7:0) TXFIFO_TX_DATA

-

N/A

Data to be sent

0x40040B0C

RF1_RXFIFO

-

(7:0) RXFIFO_RX_DATA

0x0

Received data

0x40040B10

RF1_IQFIFO

-

(7:0) IQFIFO_IQ_DATA

0x0

IQ data for AoA or AoD

0x40040B14

RF1_REG45

-

(25:16) RSSI_AVG_RSSI_AVG

0x0

Filtered RSSI value

-

(8:0) RXFIFO_COUNT_RX_COUNT

0x0

Number of bytes in the Rx FIFO

0x40040B18

RF1_DESER_STATUS

-

(7) DESER_STATUS_SIGNAL_RECEIVING

0x0

Deserializer enabling

-

(6) DESER_STATUS_SYNC_DETECTED

0x0

Sync word detection

-

(5) DESER_STATUS_WAIT_SYNC

0x0

Deserializer waiting for the sync word

-

(4) DESER_STATUS_IS_ADDRESS_BR

0x0

Received address

-

(3) DESER_STATUS_PKT_LEN_ERR

0x0

Packet length

-

(2) DESER_STATUS_ADDRESS_ERR

0x0

Address error

-

(1) DESER_STATUS_CRC_ERR

0x0

CRC error

-

(0) DESER_STATUS_DESER_FINISH

0x0

Deserializer status

0x40040B1C

RF1_BLE_AEC_CCM

-

(2) BLE_AES_CCM_BLE_AES_MIC_OK

0x0

AES CCM MIC error

-

(1) BLE_AES_CCM_BLE_AES_DONE_RX

0x0

AES CCM packet decoding

-

(0) BLE_AES_CCM_BLE_AES_DONE_TX

0x0

AES CCM packet encoding

0x40040B20

RF1_IRQ_STATUS

-

(5) IRQ_STATUS_FLAG_RXFIFO

0x0

IRQ RXFIFO status

-

(4) IRQ_STATUS_FLAG_TXFIFO

0x0

IRQ TXFIFO status

-

(3) IRQ_STATUS_FLAG_SYNC

0x0

IRQ SYNC status

-

(2) IRQ_STATUS_FLAG_RECEIVED

0x0

IRQ RECEIVED status

-

(1) IRQ_STATUS_FLAG_RXSTOP

0x0

IRQ RXSTOP status

-

(0) IRQ_STATUS_FLAG_TX

0x0

IRQ Tx status

0x40040B24

RF1_RSSI_MIN_MAX

-

(25:16) RSSI_MAX_RSSI_MAX

0x0

Maximum RSSI value over a filtering period

-

(9:0) RSSI_MIN_RSSI_MIN

0x0

Minimum RSSI value over a filtering period

0x40040B28

RF1_REG4A

-

(30:28) RX_ATT_LEVEL_RX_ATT_LEVEL_PKT_LVL

0x0

Rx attenuation level (AGC level) during the packet reception

-

(26:24) RX_ATT_LEVEL_RX_ATT_LEVEL

0x0

Rx attenuation level (AGC level)

-

(23:16) DR_ERR_IND_DR_ERR_IND

0x0

Data-rate error indicator

-

(9:0) RSSI_PKT_RSSI_PKT

0x0

Filtered RSSI value sampled during the packet reception

0x40040B2C

RF1_FEI

-

(31:16) FEI_PKT_FEI_PKT

0x0

Frequency error indicator sampled during the packet reception

-

(15:0) FEI_FEI_OUT

0x0

Frequency error indicator

0x40040B30

RF1_REG4C

-

(31:24) LINK_QUAL_PKT_LINK_QUALITY_PKT

0x0

Link quality indicator sampled during the packet reception

-

(23:16) LINK_QUAL_LINK_QUALITY

0x0

Instantaneous link quality indicator

-

(15:0) FEI_AFC_FEI_AFC

0x0

Frequency error indicator sampled during the AFC

0x40040B34

RF1_ANALOG_INFO

(25:24) BLR_READOUT_BLR_RATE

-

N/A

Bluetooth LE long range rate indicator

-

(22:20) PEAK_DET_VAL_PEAK_DET_FILT

0x0

Distance from the subband center (only available with the FLL method)

-

(18:16) PEAK_DET_VAL_PEAK_DET_RAW

0x0

Distance from the subband center (only available with the FLL method)

-

(15) ANALOG_INFO_POR_VDDA

0x0

VDDA LDO disable status

-

(14) ANALOG_INFO_PLL_UNLOCK

0x0

PLL unlock status

-

(13) ANALOG_INFO_XTAL_FINISH

0x0

XTAL algorithm status

-

(12) ANALOG_INFO_DLL_LOCKED

0x0

DLL lock status

-

(11) ANALOG_INFO_CLK_DIG_READY

0x0

Ready signal of the digital clock

-

(10) ANALOG_INFO_CLK_PLL_READY

0x0

PLL clock status

-

(9:8) ANALOG_INFO_SUBBAND

0x0

Status of the subband comparator Hi

-

(7:0) SUBBAND_ERR_SB_FLL_ERR

0x0

Distance from the subband center (only available with the FLL method)

0x40040B38

RF1_SAMPLE_RSSI

(0) SAMPLE_RSSI

-

N/A

Sample the thermometric RSSI

0x40040B3C

RF1_RSSI_THERM

-

(29:0) RSSI_THERM

0x0

Thermometric value of the RSSI

0x40040B80

RF1_LUT_ANTENNA_ARRAY_1

(31:28) LUT_ANTENNA_ARRAY_1_ANTENNA_7

(31:28) LUT_ANTENNA_ARRAY_1_ANTENNA_7

0x0

Antenna 7 specification

(27:24) LUT_ANTENNA_ARRAY_1_ANTENNA_6

(27:24) LUT_ANTENNA_ARRAY_1_ANTENNA_6

0x0

Antenna 6 specification

(23:20) LUT_ANTENNA_ARRAY_1_ANTENNA_5

(23:20) LUT_ANTENNA_ARRAY_1_ANTENNA_5

0x0

Antenna 5 specification

(19:16) LUT_ANTENNA_ARRAY_1_ANTENNA_4

(19:16) LUT_ANTENNA_ARRAY_1_ANTENNA_4

0x0

Antenna 4 specification

(15:12) LUT_ANTENNA_ARRAY_1_ANTENNA_3

(15:12) LUT_ANTENNA_ARRAY_1_ANTENNA_3

0x3

Antenna 3 specification

(11:8) LUT_ANTENNA_ARRAY_1_ANTENNA_2

(11:8) LUT_ANTENNA_ARRAY_1_ANTENNA_2

0x2

Antenna 2 specification

(7:4) LUT_ANTENNA_ARRAY_1_ANTENNA_1

(7:4) LUT_ANTENNA_ARRAY_1_ANTENNA_1

0x1

Antenna 1 specification

(3:0) LUT_ANTENNA_ARRAY_1_ANTENNA_0

(3:0) LUT_ANTENNA_ARRAY_1_ANTENNA_0

0x0

Antenna 0 specification

0x40040B84

RF1_LUT_ANTENNA_ARRAY_2

(31:28) LUT_ANTENNA_ARRAY_2_ANTENNA_15

(31:28) LUT_ANTENNA_ARRAY_2_ANTENNA_15

0x0

Antenna 15 specification

(27:24) LUT_ANTENNA_ARRAY_2_ANTENNA_14

(27:24) LUT_ANTENNA_ARRAY_2_ANTENNA_14

0x0

Antenna 14 specification

(23:20) LUT_ANTENNA_ARRAY_2_ANTENNA_13

(23:20) LUT_ANTENNA_ARRAY_2_ANTENNA_13

0x0

Antenna 13 specification

(19:16) LUT_ANTENNA_ARRAY_2_ANTENNA_12

(19:16) LUT_ANTENNA_ARRAY_2_ANTENNA_12

0x0

Antenna 12 specification

(15:12) LUT_ANTENNA_ARRAY_2_ANTENNA_11

(15:12) LUT_ANTENNA_ARRAY_2_ANTENNA_11

0x0

Antenna 11 specification

(11:8) LUT_ANTENNA_ARRAY_2_ANTENNA_10

(11:8) LUT_ANTENNA_ARRAY_2_ANTENNA_10

0x0

Antenna 10 specification

(7:4) LUT_ANTENNA_ARRAY_2_ANTENNA_9

(7:4) LUT_ANTENNA_ARRAY_2_ANTENNA_9

0x0

Antenna 9 specification

(3:0) LUT_ANTENNA_ARRAY_2_ANTENNA_8

(3:0) LUT_ANTENNA_ARRAY_2_ANTENNA_8

0x0

Antenna 8 specification

0x40040B88

RF1_LUT_ANTENNA_ARRAY_3

(31:28) LUT_ANTENNA_ARRAY_3_ANTENNA_23

(31:28) LUT_ANTENNA_ARRAY_3_ANTENNA_23

0x0

Antenna 23 specification

(27:24) LUT_ANTENNA_ARRAY_3_ANTENNA_22

(27:24) LUT_ANTENNA_ARRAY_3_ANTENNA_22

0x0

Antenna 22 specification

(23:20) LUT_ANTENNA_ARRAY_3_ANTENNA_21

(23:20) LUT_ANTENNA_ARRAY_3_ANTENNA_21

0x0

Antenna 21 specification

(19:16) LUT_ANTENNA_ARRAY_3_ANTENNA_20

(19:16) LUT_ANTENNA_ARRAY_3_ANTENNA_20

0x0

Antenna 20 specification

(15:12) LUT_ANTENNA_ARRAY_3_ANTENNA_19

(15:12) LUT_ANTENNA_ARRAY_3_ANTENNA_19

0x0

Antenna 19 specification

(11:8) LUT_ANTENNA_ARRAY_3_ANTENNA_18

(11:8) LUT_ANTENNA_ARRAY_3_ANTENNA_18

0x0

Antenna 18 specification

(7:4) LUT_ANTENNA_ARRAY_3_ANTENNA_17

(7:4) LUT_ANTENNA_ARRAY_3_ANTENNA_17

0x0

Antenna 17 specification

(3:0) LUT_ANTENNA_ARRAY_3_ANTENNA_16

(3:0) LUT_ANTENNA_ARRAY_3_ANTENNA_16

0x0

Antenna 16 specification

0x40040B8C

RF1_LUT_ANTENNA_ARRAY_4

(31:28) LUT_ANTENNA_ARRAY_4_ANTENNA_31

(31:28) LUT_ANTENNA_ARRAY_4_ANTENNA_31

0x0

Antenna 31 specification

(27:24) LUT_ANTENNA_ARRAY_4_ANTENNA_30

(27:24) LUT_ANTENNA_ARRAY_4_ANTENNA_30

0x0

Antenna 30 specification

(23:20) LUT_ANTENNA_ARRAY_4_ANTENNA_29

(23:20) LUT_ANTENNA_ARRAY_4_ANTENNA_29

0x0

Antenna 29 specification

(19:16) LUT_ANTENNA_ARRAY_4_ANTENNA_28

(19:16) LUT_ANTENNA_ARRAY_4_ANTENNA_28

0x0

Antenna 28 specification

(15:12) LUT_ANTENNA_ARRAY_4_ANTENNA_27

(15:12) LUT_ANTENNA_ARRAY_4_ANTENNA_27

0x0

Antenna 27 specification

(11:8) LUT_ANTENNA_ARRAY_4_ANTENNA_26

(11:8) LUT_ANTENNA_ARRAY_4_ANTENNA_26

0x0

Antenna 26 specification

(7:4) LUT_ANTENNA_ARRAY_4_ANTENNA_25

(7:4) LUT_ANTENNA_ARRAY_4_ANTENNA_25

0x0

Antenna 25 specification

(3:0) LUT_ANTENNA_ARRAY_4_ANTENNA_24

(3:0) LUT_ANTENNA_ARRAY_4_ANTENNA_24

0x0

Antenna 24 specification

0x40040BC0

RF1_REG50

-

(27) FEATURES_HAS_BLE_AES

0x0

Bluetooth AES block availability

-

(26) FEATURES_HAS_BLE_DF_AOA_AOD

0x1

Bluetooth Direction Finding AoA/AoD feature availability

-

(25) FEATURES_HAS_BLE_LONG_RANGE

0x1

Bluetooth long range feature availability

-

(24) FEATURES_FEATURES_AVAILABLE

0x1

Features availability

(23:16) BLR_PKT_LEN_BLR_PKT_LEN

-

N/A

Packet length of the BLR packet

(15:8) PROT_TIMER_PT_CMD

-

N/A

Protocol timer command

(0) COMMANDS_START_SUBBAND

-

N/A

Subband selection algorithm

0x40040BE0

RF1_REG51

(31:24) FSM_MODE_RM_TX

(31:24) FSM_MODE_RM_TX

0x0

Remapped register of FSM_MODE

(23:16) PA_PWR_RM

(23:16) PA_PWR_RM

0x0

Remapped register of PA_PWR

(15:8) CHANNEL_RM_TX

(15:8) CHANNEL_RM_TX

0x0

Remapped register of CHANNEL

(7:0) RATE_TX

(7:0) RATE_TX

0x0

Remapped register of BANK

0x40040BE8

RF1_REG52

(31:24) ACCESS_ADDRESS

(31:24) ACCESS_ADDRESS

0x0

Remapped register of PATTERN

(23:16) FSM_MODE_RM_RX

(23:16) FSM_MODE_RM_RX

0x0

Remapped register of FSM_MODE

(15:8) CHANNEL_RM_RX

(15:8) CHANNEL_RM_RX

0x0

Remapped register of CHANNEL

(7:0) RATE_RX

(7:0) RATE_RX

0x0

Remapped register of BANK

0x40040BF0

RF1_REG53

-

(23:16) RSSI_MAX_RM

0x0

Remapped register of RSSI_MAX

-

(15:8) RSSI_MIN_RM

0x0

Remapped register of RSSI_MIN

-

(7:0) RSSI_AVG_RM

0x0

Remapped register of RSSI_AVG

0x40040BF4

RF1_REG54

(7:0) BLR_PACKET_LEN

-

N/A

Remapped register of BLR_PACKET_LEN

0x40040BF8

RF1_REG55

-

(7:0) ITRX_FEATURES

0x0

Remapped register of ITRX_FEATURES

0x40040BFC

RF1_REG56

-

(31:24) CHIP_ID_CHIP_ID

0x30

Version of the chip

-

(23:16) MD5_REGS_MD5_REGS

0x0

MD5 calculated on the register map file

(15:8) SCAN_2_SCAN_2_PASSWORD

-

N/A

SCAN 2 key

(7:0) SCAN_1_SCAN_1_PASSWORD

-

N/A

SCAN 1 key

0x40040C00

RF2_REG00

(31) DATAWHITE_BTLE_DW_BTLE

(31) DATAWHITE_BTLE_DW_BTLE

0x1

Data whitening control

(30:24) DATAWHITE_BTLE_DW_BTLE_RST

(30:24) DATAWHITE_BTLE_DW_BTLE_RST

0x0

Reset value to put on the Bluetooth LE data whitening shift register

(23) FOURFSK_CODING_EN_FOURFSK_CODING

(23) FOURFSK_CODING_EN_FOURFSK_CODING

0x0

Enable 4FSK coding

(22:20) FOURFSK_CODING_TX_FOURFSK_CODING

(22:20) FOURFSK_CODING_TX_FOURFSK_CODING

0x0

Set the 4FSK coding (Tx mode)

(18:16) FOURFSK_CODING_RX_FOURFSK_CODING

(18:16) FOURFSK_CODING_RX_FOURFSK_CODING

0x0

Set the 4FSK decoding (Rx mode)

(14) MODE2_DIFF_CODING

(14) MODE2_DIFF_CODING

0x0

Differential coding/decoding

(13) MODE2_PSK_NFSK

(13) MODE2_PSK_NFSK

0x0

FSK/PSK mode selection

(12:8) MODE2_TESTMODE

(12:8) MODE2_TESTMODE

0x0

Output test mode

(7) MODE_NOT_TO_IDLE

(7) MODE_NOT_TO_IDLE

0x0

FSM goes in suspend mode after a Tx or Rx packet

(5) MODE_EN_FSM

(5) MODE_EN_FSM

0x1

Radio FSM control

(4) MODE_EN_DESERIALIZER

(4) MODE_EN_DESERIALIZER

0x0

Deserializer control

(3) MODE_EN_SERIALIZER

(3) MODE_EN_SERIALIZER

0x0

Serializer control

(2) MODE_TX_NRX

(2) MODE_TX_NRX

0x0

Select Tx or Rx mode

(1:0) MODE_MODE

(1:0) MODE_MODE

0x2

Select the working mode of the digital baseband

0x40040C04

RF2_REG01

(31:24) TAU_PHASE_RECOV_TAU_PHASE_RECOV

(31:24) TAU_PHASE_RECOV_TAU_PHASE_RECOV

0x14

Time constant of the fine carrier recovery block (banked)

(23:16) TAU_ROUGH_RECOV_TAU_ROUGH_RECOV

(23:16) TAU_ROUGH_RECOV_TAU_ROUGH_RECOV

0xB

Time constant of the rough carrier recovery block (banked)

(15) CARRIER_RECOVERY_EN_CORRECT_CFREQ_AFC

(15) CARRIER_RECOVERY_EN_CORRECT_CFREQ_AFC

0x0

Automatic AFC correction (banked)

(14) CARRIER_RECOVERY_CORRECT_CFREQ_IF_NEG

(14) CARRIER_RECOVERY_CORRECT_CFREQ_IF_NEG

0x0

IF correction (banked)

(13) CARRIER_RECOVERY_EN_CORRECT_CFREQ_IF

(13) CARRIER_RECOVERY_EN_CORRECT_CFREQ_IF

0x1

Automatic IF correction (banked)

(12) CARRIER_RECOVERY_AFC_NEG

(12) CARRIER_RECOVERY_AFC_NEG

0x0

AFC correction (banked)

(11) CARRIER_RECOVERY_STARTER_MODE

(11) CARRIER_RECOVERY_STARTER_MODE

0x0

Starter mode (banked)

(10) CARRIER_RECOVERY_EN_AFC

(10) CARRIER_RECOVERY_EN_AFC

0x0

Automatic frequency control (banked)

(9) CARRIER_RECOVERY_EN_FINE_RECOV

(9) CARRIER_RECOVERY_EN_FINE_RECOV

0x1

Fine carrier recovery (banked)

(8) CARRIER_RECOVERY_EN_ROUGH_RECOV

(8) CARRIER_RECOVERY_EN_ROUGH_RECOV

0x0

Rough carrier recovery (banked)

(6) MOD_TX_PULSE_NSYM

(6) MOD_TX_PULSE_NSYM

0x0

Tx pulse shape function

(5) MOD_TX_EN_INTERP

(5) MOD_TX_EN_INTERP

0x0

Tx CIC interpolator

(4:0) MOD_TX_CK_TX_M

(4:0) MOD_TX_CK_TX_M

0x0

Unsigned value determining the Tx CIC interpolator frequency

0x40040C08

RF2_REG02

(25:24) DATARATE_OFFSET_DR_LIMIT

(25:24) DATARATE_OFFSET_DR_LIMIT

0x0

Set the data-rate recovery limits

(23:16) DATARATE_OFFSET_DATARATE_OFFSET

(23:16) DATARATE_OFFSET_DATARATE_OFFSET

0x0

Data-rate offset

(15:8) TAU_DATARATE_RECOV_TAU_DATARATE_RECOV

(15:8) TAU_DATARATE_RECOV_TAU_DATARATE_RECOV

0x20

Time constant of the data-rate recovery

(7:0) TAU_CLK_RECOV_TAU_CLK_RECOV

(7:0) TAU_CLK_RECOV_TAU_CLK_RECOV

0x9

Time constant of the clock recovery (banked)

0x40040C0C

RF2_REG03

(31:30) MAC_CONF_MAC_TIMER_GR

(31:30) MAC_CONF_MAC_TIMER_GR

0x2

MAC timer granularity

(29) MAC_CONF_RX_MAC_ACT

(29) MAC_CONF_RX_MAC_ACT

0x0

Switch FSM to Rx or Tx mode after an Rx mode

(28) MAC_CONF_RX_MAC_TX_NRX

(28) MAC_CONF_RX_MAC_TX_NRX

0x0

Switch FSM to Tx mode after an Rx mode (Rx otherwise)

(27) MAC_CONF_RX_MAC_START_NSTOP

(27) MAC_CONF_RX_MAC_START_NSTOP

0x0

MAC timer activation after sync word detection

(26) MAC_CONF_TX_MAC_ACT

(26) MAC_CONF_TX_MAC_ACT

0x0

Switch FSM to Rx or Tx mode after a Tx mode

(25) MAC_CONF_TX_MAC_TX_NRX

(25) MAC_CONF_TX_MAC_TX_NRX

0x0

Switch FSM to Tx mode after a Tx mode (Rx otherwise)

(24) MAC_CONF_TX_MAC_START_NSTOP

(24) MAC_CONF_TX_MAC_START_NSTOP

0x0

MAC timer activation after packet transmission

(23) IRQ_CONF_IRQ_HIGH_Z

(23) IRQ_CONF_IRQ_HIGH_Z

0x0

Pads are set to high-Z when the IRQ is not active

(22) IRQ_CONF_IRQ_ACTIVE_LOW

(22) IRQ_CONF_IRQ_ACTIVE_LOW

0x1

IRQ are active low

(21:16) IRQ_CONF_IRQS_MASK

(21:16) IRQ_CONF_IRQS_MASK

0x0

Mask to determine which IRQs are enabled (active high)

(15:13) FIFO_2_FIFO_THR_TX

(15:13) FIFO_2_FIFO_THR_TX

0x0

Threshold indicating the "almost empty" Tx FIFO state

(12) FIFO_2_WAIT_TXFIFO_WR

(12) FIFO_2_WAIT_TXFIFO_WR

0x0

FSM will wait a Tx FIFO write before starting the Tx mode in case of an empty Tx FIFO

(11) FIFO_2_STOP_ON_RXFF_OVFLW

(11) FIFO_2_STOP_ON_RXFF_OVFLW

0x0

Stop the reception in case of a FIFO overflow

(10) FIFO_2_STOP_ON_TXFF_UNFLW

(10) FIFO_2_STOP_ON_TXFF_UNFLW

0x0

Stop the transmission in case of a FIFO underflow

(9) FIFO_2_RXFF_FLUSH_ON_START

(9) FIFO_2_RXFF_FLUSH_ON_START

0x1

Flush the Rx FIFO when the Rx mode is enabled in order to receive a packet with an empty FIFO

(8) FIFO_2_TXFF_FLUSH_ON_STOP

(8) FIFO_2_TXFF_FLUSH_ON_STOP

0x1

Flush the Tx FIFO after the end of a packet transmission in order to have an empty FIFO

(7) FIFO_FIFO_FLUSH_ON_OVFLW

(7) FIFO_FIFO_FLUSH_ON_OVFLW

0x0

Overflow FIFO flush control

(6) FIFO_FIFO_FLUSH_ON_ADDR_ERR

(6) FIFO_FIFO_FLUSH_ON_ADDR_ERR

0x0

Address error FIFO flush control

(5) FIFO_FIFO_FLUSH_ON_PL_ERR

(5) FIFO_FIFO_FLUSH_ON_PL_ERR

0x0

Packet length error FIFO flush control

(4) FIFO_FIFO_FLUSH_ON_CRC_ERR

(4) FIFO_FIFO_FLUSH_ON_CRC_ERR

0x1

CRC error FIFO flush control

(3) FIFO_RX_FIFO_ACK

(3) FIFO_RX_FIFO_ACK

0x0

Rx FIFO acknowledgement

(2:0) FIFO_FIFO_THR

(2:0) FIFO_FIFO_THR

0x0

Threshold indicating the "almost full" Rx FIFO state

0x40040C10

RF2_PADS_03

(28:24) PAD_CONF_1_PAD_3_CONF

(28:24) PAD_CONF_1_PAD_3_CONF

0x0

Configuration of GPIO pad 3

(20:16) PAD_CONF_1_PAD_2_CONF

(20:16) PAD_CONF_1_PAD_2_CONF

0x0

Configuration of GPIO pad 2

(12:8) PAD_CONF_1_PAD_1_CONF

(12:8) PAD_CONF_1_PAD_1_CONF

0x0

Configuration of GPIO pad 1

(4:0) PAD_CONF_1_PAD_0_CONF

(4:0) PAD_CONF_1_PAD_0_CONF

0x0

Configuration of GPIO pad 0

0x40040C14

RF2_PADS_47

(28:24) PAD_CONF_2_PAD_7_CONF

(28:24) PAD_CONF_2_PAD_7_CONF

0x0

Configuration of GPIO pad 7

(20:16) PAD_CONF_2_PAD_6_CONF

(20:16) PAD_CONF_2_PAD_6_CONF

0x0

Configuration of GPIO pad 6

(12:8) PAD_CONF_2_PAD_5_CONF

(12:8) PAD_CONF_2_PAD_5_CONF

0x0

Configuration of GPIO pad 5

(4:0) PAD_CONF_2_PAD_4_CONF

(4:0) PAD_CONF_2_PAD_4_CONF

0x0

Configuration of GPIO pad 4

0x40040C18

RF2_CENTER_FREQ

(31) CENTER_FREQ_ADAPT_CFREQ

(31) CENTER_FREQ_ADAPT_CFREQ

0x1

Frequency adaptation between Tx and Rx modes

(30) CENTER_FREQ_RX_DIV_5_N6

(30) CENTER_FREQ_RX_DIV_5_N6

0x0

Ratio of the PLL reference between Tx and Rx modes

(29:0) CENTER_FREQ_CENTER_FREQUENCY

(29:0) CENTER_FREQ_CENTER_FREQUENCY

0x215C71B

Set the center frequency

0x40040C1C

RF2_PADS_89

(31:24) TX_MAC_TIMER_TX_MAC_TIMER

(31:24) TX_MAC_TIMER_TX_MAC_TIMER

0x82

Time to wait after the Tx mode

(23:16) RX_MAC_TIMER_RX_MAC_TIMER

(23:16) RX_MAC_TIMER_RX_MAC_TIMER

0x23

Time to wait after the Rx mode

(12:8) PAD_CONF_3_PAD_9_CONF

(12:8) PAD_CONF_3_PAD_9_CONF

0x0

Configuration of GPIO pad 9

(4:0) PAD_CONF_3_PAD_8_CONF

(4:0) PAD_CONF_3_PAD_8_CONF

0x0

Configuration of GPIO pad 8

0x40040C20

RF2_REG08

(31:30) MOD_INFO_RX_DIV_CK_RX

(31:30) MOD_INFO_RX_DIV_CK_RX

0x0

Set the clock divider for the Rx mode (banked)

(29) MOD_INFO_RX_SYMBOL_2BIT_RX

(29) MOD_INFO_RX_SYMBOL_2BIT_RX

0x0

Rx symbol bits composition (banked)

(28:24) MOD_INFO_RX_DR_M_RX

(28:24) MOD_INFO_RX_DR_M_RX

0x0

Unsigned value determining the oversampling frequency and consequently the data-rate (banked)

(23:22) MOD_INFO_TX_DIV_CK_TX

(23:22) MOD_INFO_TX_DIV_CK_TX

0x0

Set the clock divider for the Tx mode (banked)

(21) MOD_INFO_TX_SYMBOL_2BIT_TX

(21) MOD_INFO_TX_SYMBOL_2BIT_TX

0x0

Tx symbol bits composition (banked)

(20:16) MOD_INFO_TX_DR_M_TX

(20:16) MOD_INFO_TX_DR_M_TX

0x0

Unsigned value determining the oversampling frequency and consequently the data-rate (banked)

(14) CHANNEL_SWITCH_IQ

(14) CHANNEL_SWITCH_IQ

0x0

Switch I and Q channels

(13:8) CHANNEL_CHANNEL

(13:8) CHANNEL_CHANNEL

0x0

Channel number

(3) BANK_DATARATE_TX_NRX

(3) BANK_DATARATE_TX_NRX

0x0

Select the data-rate register

(2) BANK_STD_BLE_RATES

(2) BANK_STD_BLE_RATES

0x0

Select the actual bank behavior

(1:0) BANK_BANK

(1:0) BANK_BANK

0x0

Select the used bank

0x40040C24

RF2_CODING

(31) CODING_EN_DATAWHITE

(31) CODING_EN_DATAWHITE

0x1

Data-whitening enabling (banked)

(30) CODING_I_NQ_DELAYED

(30) CODING_I_NQ_DELAYED

0x0

Channel I delay (banked)

(29) CODING_OFFSET

(29) CODING_OFFSET

0x0

Offset (delay) introduction (banked)

(28) CODING_BIT_INVERT

(28) CODING_BIT_INVERT

0x0

Bit value inversion in Tx and Rx modes (banked)

(27) CODING_EVEN_BEFORE_ODD

(27) CODING_EVEN_BEFORE_ODD

0x0

Determine the bit order in case of a 2 bits per symbol modulation (banked)

(26) CODING_EN_802154_L2F

(26) CODING_EN_802154_L2F

0x0

Linear to frequency encoding needed in order to modulate an OQPSK as an MSK (banked)

(25) CODING_EN_802154_B2C

(25) CODING_EN_802154_B2C

0x0

Bit to chips encoding used in the IEEE 802.15.4 standard (banked)

(24) CODING_EN_MANCHESTER

(24) CODING_EN_MANCHESTER

0x0

Manchester encoding (banked)

(23) CHANNELS_2_EN_CHANNEL_SEL

(23) CHANNELS_2_EN_CHANNEL_SEL

0x1

Definition of channels (banked)

(22) CHANNELS_2_EN_CHN_BLE

(22) CHANNELS_2_EN_CHN_BLE

0x1

BLE channels index LUT (banked)

(19:16) CHANNELS_2_CHANNEL_SPACING_HI

(19:16) CHANNELS_2_CHANNEL_SPACING_HI

0x7

Channel spacing MSB (banked)

(15:0) CHANNELS_1_CHANNEL_SPACING_LO

(15:0) CHANNELS_1_CHANNEL_SPACING_LO

0x1C72

Channel spacing LSB (banked)

0x40040C28

RF2_PACKET_HANDLING

(31:24) PREAMBLE_PREAMBLE

(31:24) PREAMBLE_PREAMBLE

0x55

Preamble to be inserted (banked)

(22) PACKET_LENGTH_OPTS_EN_PACKET_LEN_FIX

(22) PACKET_LENGTH_OPTS_EN_PACKET_LEN_FIX

0x0

Packet length configuration (banked)

(21:18) PACKET_LENGTH_OPTS_PACKET_LEN_CORR

(21:18) PACKET_LENGTH_OPTS_PACKET_LEN_CORR

0x0

Signed value specifying the correction to apply to the specified packet length (banked)

(17:16) PACKET_LENGTH_OPTS_PACKET_LEN_POS

(17:16) PACKET_LENGTH_OPTS_PACKET_LEN_POS

0x1

Unsigned value that specifies the position of the packet length after the pattern (banked)

(15:8) PACKET_LENGTH_PACKET_LEN

(15:8) PACKET_LENGTH_PACKET_LEN

0xFF

The packet length in the fixed packet length mode (banked)

(7) PACKET_HANDLING_LSB_FIRST

(7) PACKET_HANDLING_LSB_FIRST

0x1

Select LSB or MSB to send first (banked)

(6) PACKET_HANDLING_EN_CRC

(6) PACKET_HANDLING_EN_CRC

0x1

Automatic CRC evaluation and insertion (banked)

(5) PACKET_HANDLING_EN_CRC_ON_PKTLEN

(5) PACKET_HANDLING_EN_CRC_ON_PKTLEN

0x1

CRC calculation on the packet length part of the packet (banked)

(4) PACKET_HANDLING_EN_PREAMBLE

(4) PACKET_HANDLING_EN_PREAMBLE

0x1

Automatic preamble insertion (banked)

(3) PACKET_HANDLING_EN_MULTI_FRAME

(3) PACKET_HANDLING_EN_MULTI_FRAME

0x0

Multi-frame packet (banked)

(2) PACKET_HANDLING_ENB_DW_ON_CRC

(2) PACKET_HANDLING_ENB_DW_ON_CRC

0x0

Data-whitening on the CRC disabling (banked)

(1) PACKET_HANDLING_EN_PATTERN

(1) PACKET_HANDLING_EN_PATTERN

0x1

Automatic pattern insertion and recognition (banked)

(0) PACKET_HANDLING_EN_PACKET

(0) PACKET_HANDLING_EN_PACKET

0x1

Packet handler enabling (banked)

0x40040C2C

RF2_SYNC_PATTERN

(31:0) PATTERN

(31:0) PATTERN

0x8E89BED6

Pattern (sync word) to be inserted or recognized (banked)

0x40040C30

RF2_REG0C

(31:16) ADDRESS_ADDRESS

(31:16) ADDRESS_ADDRESS

0x0

Address of the node (banked)

(11) ADDRESS_CONF_ADDRESS_LEN

(11) ADDRESS_CONF_ADDRESS_LEN

0x0

Address length selection (banked)

(10) ADDRESS_CONF_EN_ADDRESS_RX_BR

(10) ADDRESS_CONF_EN_ADDRESS_RX_BR

0x0

Broadcast address detection in Rx mode (banked)

(9) ADDRESS_CONF_EN_ADDRESS_RX

(9) ADDRESS_CONF_EN_ADDRESS_RX

0x0

Address detection in Rx mode (banked)

(8) ADDRESS_CONF_EN_ADDRESS_TX

(8) ADDRESS_CONF_EN_ADDRESS_TX

0x0

Address insertion in Tx mode (banked)

(7:0) PREAMBLE_LENGTH_PREAMBLE_LEN

(7:0) PREAMBLE_LENGTH_PREAMBLE_LEN

0x0

Length of the preamble -1 (banked)

0x40040C34

RF2_PACKET_EXTRA

(29:28) CONV_CODES_CONF_STOP_WORD_LEN

(29:28) CONV_CODES_CONF_STOP_WORD_LEN

0x0

Length of the stop word (banked)

(27:26) CONV_CODES_CONF_CC_VITERBI_LEN

(27:26) CONV_CODES_CONF_CC_VITERBI_LEN

0x2

Set the memory length of the Viterbi decoder (banked)

(25) CONV_CODES_CONF_CC_EN_TX_STOP

(25) CONV_CODES_CONF_CC_EN_TX_STOP

0x0

Stop word at the end of the transmission (banked)

(24) CONV_CODES_CONF_EN_CONV_CODE

(24) CONV_CODES_CONF_EN_CONV_CODE

0x0

Convolutional codes (banked)

(22) PACKET_EXTRA_FIFO_REWIND

(22) PACKET_EXTRA_FIFO_REWIND

0x0

Rewind the FIFO to the initial stage at the end of a Tx transmission (banked)

(21) PACKET_EXTRA_BLE_PREAMBLE

(21) PACKET_EXTRA_BLE_PREAMBLE

0x1

Handle the preamble directly in Tx mode (PREAMBLE register is not used) according to the BLE standard (banked)

(20) PACKET_EXTRA_PKT_INFO_PRE_NPOST

(20) PACKET_EXTRA_PKT_INFO_PRE_NPOST

0x0

Packet information sampling (banked)

(19:18) PACKET_EXTRA_PATTERN_MAX_ERR

(19:18) PACKET_EXTRA_PATTERN_MAX_ERR

0x0

Unsigned value that specifies the maximum number of errors in the pattern recognition (banked)

(17:16) PACKET_EXTRA_PATTERN_WORD_LEN

(17:16) PACKET_EXTRA_PATTERN_WORD_LEN

0x3

Pattern word length (banked)

(15:0) ADDRESS_BROADCAST_ADDRESS_BR

(15:0) ADDRESS_BROADCAST_ADDRESS_BR

0x0

Broadcast address (banked)

0x40040C38

RF2_CRC_POLYNOMIAL

(31:0) CRC_POLY

(31:0) CRC_POLY

0x80032D

CRC polynomial (banked)

0x40040C3C

RF2_CRC_RST

(31:0) CRC_RST

(31:0) CRC_RST

0x555555

CRC reset value (banked)

0x40040C40

RF2_REG10

(25:21) CONV_CODES_PUNCT_CC_PUNCT_1

(25:21) CONV_CODES_PUNCT_CC_PUNCT_1

0x1

Puncture of the second convolutional code (banked)

(20:16) CONV_CODES_PUNCT_CC_PUNCT_0

(20:16) CONV_CODES_PUNCT_CC_PUNCT_0

0x1

Puncture of the first convolutional code (banked)

(11) FRAC_CONF_TX_FRAC_GAIN

(11) FRAC_CONF_TX_FRAC_GAIN

0x0

Additional gain for fractional data-rates in Tx mode (banked)

(10) FRAC_CONF_RX_FRAC_GAIN

(10) FRAC_CONF_RX_FRAC_GAIN

0x0

Additional gain for fractional data-rates in Rx mode (banked)

(9) FRAC_CONF_TX_EN_FRAC

(9) FRAC_CONF_TX_EN_FRAC

0x0

Fractional data-rates in Tx mode (banked)

(8) FRAC_CONF_RX_EN_FRAC

(8) FRAC_CONF_RX_EN_FRAC

0x0

Fractional data-rates in Rx mode (banked)

(7:4) CONV_CODES_POLY_CC_POLY_1

(7:4) CONV_CODES_POLY_CC_POLY_1

0xD

Second convolutional code (banked)

(3:0) CONV_CODES_POLY_CC_POLY_0

(3:0) CONV_CODES_POLY_CC_POLY_0

0xF

First convolutional code (banked)

0x40040C44

RF2_REG11

(31) FILTER_GAIN_LIN_FILTER

(31) FILTER_GAIN_LIN_FILTER

0x0

Enable the linear filtering (banked)

(30) FILTER_GAIN_LOW_LIN_GAIN

(30) FILTER_GAIN_LOW_LIN_GAIN

0x0

Reduce the total gain by two if the linear gain is set (banked)

(29:27) FILTER_GAIN_GAIN_M

(29:27) FILTER_GAIN_GAIN_M

0x0

Mantissa of the final stage gain of the matched filter (banked)

(26:24) FILTER_GAIN_GAIN_E

(26:24) FILTER_GAIN_GAIN_E

0x0

Exponent of the final stage gain of the matched filter (banked)

(23:20) TX_MULT_TX_MULT_EXP

(23:20) TX_MULT_TX_MULT_EXP

0x2

Exponent of the Tx multiplier (banked)

(19:16) TX_MULT_TX_MULT_MAN

(19:16) TX_MULT_TX_MULT_MAN

0x9

Mantissa of the Tx multiplier (banked)

(15:12) TX_FRAC_CONF_TX_FRAC_DEN

(15:12) TX_FRAC_CONF_TX_FRAC_DEN

0x0

Denominator of the fractional data-rate in Tx mode (banked)

(11:8) TX_FRAC_CONF_TX_FRAC_NUM

(11:8) TX_FRAC_CONF_TX_FRAC_NUM

0x0

Numerator of the fractional data-rate in Tx mode (banked)

(7:4) RX_FRAC_CONF_RX_FRAC_DEN

(7:4) RX_FRAC_CONF_RX_FRAC_DEN

0x0

Denominator of the fractional data-rate in Rx mode (banked)

(3:0) RX_FRAC_CONF_RX_FRAC_NUM

(3:0) RX_FRAC_CONF_RX_FRAC_NUM

0x0

Numerator of the fractional data-rate in Rx mode (banked)

0x40040C48

RF2_TX_PULSE_SHAPE_1

(31:24) TX_PULSE_SHAPE_1_TX_COEF4

(31:24) TX_PULSE_SHAPE_1_TX_COEF4

0x0

Tx pulse shape coefficient 4 (banked)

(23:16) TX_PULSE_SHAPE_1_TX_COEF3

(23:16) TX_PULSE_SHAPE_1_TX_COEF3

0x0

Tx pulse shape coefficient 3 (banked)

(15:8) TX_PULSE_SHAPE_1_TX_COEF2

(15:8) TX_PULSE_SHAPE_1_TX_COEF2

0x0

Tx pulse shape coefficient 2 (banked)

(7:0) TX_PULSE_SHAPE_1_TX_COEF1

(7:0) TX_PULSE_SHAPE_1_TX_COEF1

0x0

Tx pulse shape coefficient 1 (banked)

0x40040C4C

RF2_TX_PULSE_SHAPE_2

(31:24) TX_PULSE_SHAPE_2_TX_COEF8

(31:24) TX_PULSE_SHAPE_2_TX_COEF8

0x2

Tx pulse shape coefficient 8 (banked)

(23:16) TX_PULSE_SHAPE_2_TX_COEF7

(23:16) TX_PULSE_SHAPE_2_TX_COEF7

0x1

Tx pulse shape coefficient 7 (banked)

(15:8) TX_PULSE_SHAPE_2_TX_COEF6

(15:8) TX_PULSE_SHAPE_2_TX_COEF6

0x0

Tx pulse shape coefficient 6 (banked)

(7:0) TX_PULSE_SHAPE_2_TX_COEF5

(7:0) TX_PULSE_SHAPE_2_TX_COEF5

0x0

Tx pulse shape coefficient 5 (banked)

0x40040C50

RF2_TX_PULSE_SHAPE_3

(31:24) TX_PULSE_SHAPE_3_TX_COEF12

(31:24) TX_PULSE_SHAPE_3_TX_COEF12

0x36

Tx pulse shape coefficient 12 (banked)

(23:16) TX_PULSE_SHAPE_3_TX_COEF11

(23:16) TX_PULSE_SHAPE_3_TX_COEF11

0x20

Tx pulse shape coefficient 11 (banked)

(15:8) TX_PULSE_SHAPE_3_TX_COEF10

(15:8) TX_PULSE_SHAPE_3_TX_COEF10

0x10

Tx pulse shape coefficient 10 (banked)

(7:0) TX_PULSE_SHAPE_3_TX_COEF9

(7:0) TX_PULSE_SHAPE_3_TX_COEF9

0x7

Tx pulse shape coefficient 9 (banked)

0x40040C54

RF2_TX_PULSE_SHAPE_4

(31:24) TX_PULSE_SHAPE_4_TX_COEF16

(31:24) TX_PULSE_SHAPE_4_TX_COEF16

0x7D

Tx pulse shape coefficient 16 (banked)

(23:16) TX_PULSE_SHAPE_4_TX_COEF15

(23:16) TX_PULSE_SHAPE_4_TX_COEF15

0x75

Tx pulse shape coefficient 15 (banked)

(15:8) TX_PULSE_SHAPE_4_TX_COEF14

(15:8) TX_PULSE_SHAPE_4_TX_COEF14

0x66

Tx pulse shape coefficient 14 (banked)

(7:0) TX_PULSE_SHAPE_4_TX_COEF13

(7:0) TX_PULSE_SHAPE_4_TX_COEF13

0x4F

Tx pulse shape coefficient 13 (banked)

0x40040C58

RF2_FRONTEND

(25:16) RX_IF_DIG_IF_DIG

(25:16) RX_IF_DIG_IF_DIG

0x40

IF frequency (banked)

(14:11) FRONTEND_RESAMPLE_PH_GAIN

(14:11) FRONTEND_RESAMPLE_PH_GAIN

0x6

Gain of the phase resampling block (banked)

(10:8) FRONTEND_RESAMPLE_RSSI_G2

(10:8) FRONTEND_RESAMPLE_RSSI_G2

0x0

Gain of the decimator in the RSSI resampling block (banked)

(7:6) FRONTEND_RESAMPLE_RSSI_G1

(7:6) FRONTEND_RESAMPLE_RSSI_G1

0x0

Gain of the interpolator in the RSSI resampling block (banked)

(5) FRONTEND_EN_RESAMPLE_RSSI

(5) FRONTEND_EN_RESAMPLE_RSSI

0x0

RSSI resampling (banked)

(4) FRONTEND_EN_RESAMPLE_PHADC

(4) FRONTEND_EN_RESAMPLE_PHADC

0x1

Phase resampling (banked)

(3:0) FRONTEND_DIV_PHADC

(3:0) FRONTEND_DIV_PHADC

0x0

Unsigned value that specifies the divider to obtain the phase ADC clock and RSSI (banked)

0x40040C5C

RF2_RX_PULSE_SHAPE

(31:28) RX_PULSE_SHAPE_RX_COEF8

(31:28) RX_PULSE_SHAPE_RX_COEF8

0xF

Rx pulse shape coefficient 8 (banked)

(27:24) RX_PULSE_SHAPE_RX_COEF7

(27:24) RX_PULSE_SHAPE_RX_COEF7

0xE

Rx pulse shape coefficient 7 (banked)

(23:20) RX_PULSE_SHAPE_RX_COEF6

(23:20) RX_PULSE_SHAPE_RX_COEF6

0xC

Rx pulse shape coefficient 6 (banked)

(19:16) RX_PULSE_SHAPE_RX_COEF5

(19:16) RX_PULSE_SHAPE_RX_COEF5

0xA

Rx pulse shape coefficient 5 (banked)

(15:12) RX_PULSE_SHAPE_RX_COEF4

(15:12) RX_PULSE_SHAPE_RX_COEF4

0x7

Rx pulse shape coefficient 4 (banked)

(11:8) RX_PULSE_SHAPE_RX_COEF3

(11:8) RX_PULSE_SHAPE_RX_COEF3

0x4

Rx pulse shape coefficient 3 (banked)

(7:4) RX_PULSE_SHAPE_RX_COEF2

(7:4) RX_PULSE_SHAPE_RX_COEF2

0x2

Rx pulse shape coefficient 2 (banked)

(3:0) RX_PULSE_SHAPE_RX_COEF1

(3:0) RX_PULSE_SHAPE_RX_COEF1

0x1

Rx pulse shape coefficient 1 (banked)

0x40040C60

RF2_REG18

(28) DELAY_LINE_CONF_MULTI_SYNC

(28) DELAY_LINE_CONF_MULTI_SYNC

0x0

Detect multiple syncs (banked)

(27:25) DELAY_LINE_CONF_DL_ISI_THR

(27:25) DELAY_LINE_CONF_DL_ISI_THR

0x1

Threshold bias for ISI compensation in the delay line sync word comparator (banked)

(22) DELAY_LINE_CONF_EN_SYNC_OK_DELAY_LINE

(22) DELAY_LINE_CONF_EN_SYNC_OK_DELAY_LINE

0x1

Use pattern_ok signal in delay line to synchronize the deserializer (banked)

(21:20) DELAY_LINE_CONF_MAX_ERR_IN_DL_SYNC

(21:20) DELAY_LINE_CONF_MAX_ERR_IN_DL_SYNC

0x0

Set the maximum errors in the delay line sync detection (banked)

(19) DELAY_LINE_CONF_EN_NOT_CAUSAL

(19) DELAY_LINE_CONF_EN_NOT_CAUSAL

0x0

Non causal processing (banked)

(18:16) DELAY_LINE_CONF_NC_SEL_OUT

(18:16) DELAY_LINE_CONF_NC_SEL_OUT

0x0

Select the output position for the non causal processing (banked)

(15:8) FSK_FCR_AMP_1_FSK_FCR_AMP1

(15:8) FSK_FCR_AMP_1_FSK_FCR_AMP1

0x1B

FSK amplitude low (banked)

(6:4) CARRIER_RECOVERY_EXTRA_FREQ_LIMIT_MAN

(6:4) CARRIER_RECOVERY_EXTRA_FREQ_LIMIT_MAN

0x5

Mantissa of the carrier recovery frequency limit (banked)

(2:0) CARRIER_RECOVERY_EXTRA_FREQ_LIMIT_EXP

(2:0) CARRIER_RECOVERY_EXTRA_FREQ_LIMIT_EXP

0x0

Exponent of the carrier recovery frequency limit (banked)

0x40040C64

RF2_REG19

(30) RSSI_BANK_EN_RSSI_DITHER

(30) RSSI_BANK_EN_RSSI_DITHER

0x0

Speed on the RSSI triangular dithering signal (banked)

(29) RSSI_BANK_FAST_RSSI

(29) RSSI_BANK_FAST_RSSI

0x0

RSSI filtering speed (banked)

(28) RSSI_BANK_EN_FAST_PRE_SYNC

(28) RSSI_BANK_EN_FAST_PRE_SYNC

0x1

Fast mode switching during the preamble reception (banked)

(27:24) RSSI_BANK_TAU_RSSI_FILTERING

(27:24) RSSI_BANK_TAU_RSSI_FILTERING

0x1

Time constant of the RSSI filtering block (banked)

(20) DECISION_USE_VIT_SOFT

(20) DECISION_USE_VIT_SOFT

0x0

Viterbi soft decoding (banked)

(19:18) DECISION_VITERBI_LEN

(19:18) DECISION_VITERBI_LEN

0x2

Set the Viterbi path length (banked)

(17) DECISION_VITERBI_POW_NLIN

(17) DECISION_VITERBI_POW_NLIN

0x1

Viterbi algorithm uses power instead of amplitude to evaluate the error on the path (banked)

(16) DECISION_EN_VITERBI_GFSK

(16) DECISION_EN_VITERBI_GFSK

0x1

Viterbi algorithm for the GFSK decoding (banked)

(15:8) FSK_FCR_AMP_3_FSK_FCR_AMP3

(15:8) FSK_FCR_AMP_3_FSK_FCR_AMP3

0x44

FSK amplitude high (banked)

(7:0) FSK_FCR_AMP_2_FSK_FCR_AMP2

(7:0) FSK_FCR_AMP_2_FSK_FCR_AMP2

0x30

FSK amplitude mid (banked)

0x40040C68

RF2_REG1A

(28:24) PA_PWR_PA_PWR

(28:24) PA_PWR_PA_PWR

0xC

Signed value that sets the PA power

(22) RSSI_BANK_ALT_USE_RSSI_ALT

(22) RSSI_BANK_ALT_USE_RSSI_ALT

0x0

Use alternative RRSI configuration (banked)

(21) RSSI_BANK_ALT_FAST_RSSI_ALT

(21) RSSI_BANK_ALT_FAST_RSSI_ALT

0x0

RSSI filtering speed (banked)

(19:16) RSSI_BANK_ALT_TAU_RSSI_FILTERING_ALT

(19:16) RSSI_BANK_ALT_TAU_RSSI_FILTERING_ALT

0x3

Time constant of the RSSI filtering block (banked)

(15:0) CORRECT_CFREQ_IF_CORRECT_CFREQ_IF

(15:0) CORRECT_CFREQ_IF_CORRECT_CFREQ_IF

0x1555

Unsigned value that specifies the IF for the Rx mode (banked)

0x40040C6C

RF2_REG1B

(31) PLL_BANK_EN_LOW_CHP_BIAS_TX

(31) PLL_BANK_EN_LOW_CHP_BIAS_TX

0x0

Set the en_low_chp_bias bit in Tx mode (banked)

(30) PLL_BANK_EN_LOW_CHP_BIAS_RX

(30) PLL_BANK_EN_LOW_CHP_BIAS_RX

0x1

Set the en_low_chp_bias bit in Rx mode (banked)

(29:28) PLL_BANK_PLL_FILTER_RES_TRIM_TX

(29:28) PLL_BANK_PLL_FILTER_RES_TRIM_TX

0x3

Modify the value of the loop filter resistor R2 when bit 5 is high in Tx mode (banked)

(27:24) PLL_BANK_IQ_PLL_0_TX

(27:24) PLL_BANK_IQ_PLL_0_TX

0x4

Charge pump bias for Tx case (banked)

(22) PLL_BANK_LOW_DR_TX

(22) PLL_BANK_LOW_DR_TX

0x0

Enable low data-rate mode in Tx mode (banked)

(21:20) PLL_BANK_PLL_FILTER_RES_TRIM_RX

(21:20) PLL_BANK_PLL_FILTER_RES_TRIM_RX

0x0

Modify the value of the loop filter resistor R2 when bit 5 is high in Rx mode (banked)

(19:16) PLL_BANK_IQ_PLL_0_RX

(19:16) PLL_BANK_IQ_PLL_0_RX

0xB

Charge pump bias for Rx (banked)

(15) ANACLK_USE_NEW_ANACK

(15) ANACLK_USE_NEW_ANACK

0x0

Use the new analog clock generator (banked)

(13:12) ANACLK_DIV_CK_RSSI

(13:12) ANACLK_DIV_CK_RSSI

0x0

Set the master clock divider for the RSSI clock (banked)

(11:10) ANACLK_DIV_CK_FILT

(11:10) ANACLK_DIV_CK_FILT

0x0

Set the master clock divider for the channel filter clock (banked)

(9:8) ANACLK_DIV_CK_PHADC

(9:8) ANACLK_DIV_CK_PHADC

0x0

Set the master clock divider for the phase ADC clock (banked)

(7:4) ANACLK_DIV_RSSI

(7:4) ANACLK_DIV_RSSI

0x1

Unsigned value that specifies the division factor for the clock controlling the RSSI (banked)

(3:0) ANACLK_DIV_FILT

(3:0) ANACLK_DIV_FILT

0x5

Unsigned value that specifies the division factor for the clock controlling the channel filter (banked)

0x40040C70

RF2_RSSI_CTRL

(31:30) RSSI_CTRL_AGC_DECAY_TAU

(31:30) RSSI_CTRL_AGC_DECAY_TAU

0x3

Time constant of the decay speed

(29) RSSI_CTRL_AGC_USE_LNA

(29) RSSI_CTRL_AGC_USE_LNA

0x1

AGC algorithm uses LNA bias

(28) RSSI_CTRL_AGC_MODE

(28) RSSI_CTRL_AGC_MODE

0x1

AGC algorithm selection

(27:26) RSSI_CTRL_AGC_WAIT

(27:26) RSSI_CTRL_AGC_WAIT

0x3

Set the wait time of the AGC after switching between state

(25) RSSI_CTRL_PAYLOAD_BLOCKS_AGC

(25) RSSI_CTRL_PAYLOAD_BLOCKS_AGC

0x1

AGC payload blocking

(24) RSSI_CTRL_BYPASS_AGC

(24) RSSI_CTRL_BYPASS_AGC

0x0

AGC algorithm bypass

(20:16) PA_PWR_OFFSET_PA_PWR_OFFSET

(20:16) PA_PWR_OFFSET_PA_PWR_OFFSET

0x0

Signed value that sets the PA power (banked)

(12:8) FILTER_BIAS_IQ_FI_BW

(12:8) FILTER_BIAS_IQ_FI_BW

0x14

Bias for the bandwidth of the channel filter (banked)

(4:0) FILTER_BIAS_IQ_FI_FC

(4:0) FILTER_BIAS_IQ_FI_FC

0xB

Bias for the central frequency of the channel filter (banked)

0x40040C74

RF2_REG1D

(31:28) AGC_PEAK_DET_PEAK_DET_TAU

(31:28) AGC_PEAK_DET_PEAK_DET_TAU

0x7

Time constant of the peak detector monostable circuit

(27:26) AGC_PEAK_DET_PEAK_DET_THR_LOW

(27:26) AGC_PEAK_DET_PEAK_DET_THR_LOW

0x0

Threshold for the low level of the peak detector

(25) AGC_PEAK_DET_PEAK_DET_THR_HIGH

(25) AGC_PEAK_DET_PEAK_DET_THR_HIGH

0x0

Threshold for the high level of the peak detector

(24) AGC_PEAK_DET_EN_AGC_PEAK

(24) AGC_PEAK_DET_EN_AGC_PEAK

0x1

Enable AGC peak detector

(23:16) AGC_THR_HIGH_AGC_THR_HIGH

(23:16) AGC_THR_HIGH_AGC_THR_HIGH

0x69

AGC threshold high level (banked)

(15:8) AGC_THR_LOW_AGC_THR_LOW

(15:8) AGC_THR_LOW_AGC_THR_LOW

0x40

AGC threshold low level (banked)

(7:4) ATT_CTRL_ATT_CTRL_MAX

(7:4) ATT_CTRL_ATT_CTRL_MAX

0xB

Maximum attenuation level in AGC algorithm

(3:0) ATT_CTRL_SET_RX_ATT_CTRL

(3:0) ATT_CTRL_SET_RX_ATT_CTRL

0x0

Attenuation level if the AGC is bypassed

0x40040C78

RF2_AGC_LUT1

(31:22) AGC_LUT_1_AGC_LEVEL_2_LO

(31:22) AGC_LUT_1_AGC_LEVEL_2_LO

0x280

AGC values level 2 (LSB)

(21:11) AGC_LUT_1_AGC_LEVEL_1

(21:11) AGC_LUT_1_AGC_LEVEL_1

0x80

AGC values level 1

(10:0) AGC_LUT_1_AGC_LEVEL_0

(10:0) AGC_LUT_1_AGC_LEVEL_0

0x0

AGC values level 0

0x40040C7C

RF2_AGC_LUT2

(31:23) AGC_LUT_2_AGC_LEVEL_5_LO

(31:23) AGC_LUT_2_AGC_LEVEL_5_LO

0x84

AGC values level 5 (LSB)

(22:12) AGC_LUT_2_AGC_LEVEL_4

(22:12) AGC_LUT_2_AGC_LEVEL_4

0x284

AGC values level 4

(11:1) AGC_LUT_2_AGC_LEVEL_3

(11:1) AGC_LUT_2_AGC_LEVEL_3

0x480

AGC values level 3

(0) AGC_LUT_2_AGC_LEVEL_2_HI

(0) AGC_LUT_2_AGC_LEVEL_2_HI

0x0

AGC values level 2 (MSB)

0x40040C80

RF2_AGC_LUT3

(31:24) AGC_LUT_3_AGC_LEVEL_8_LO

(31:24) AGC_LUT_3_AGC_LEVEL_8_LO

0x9D

AGC values level 8 (LSB)

(23:13) AGC_LUT_3_AGC_LEVEL_7

(23:13) AGC_LUT_3_AGC_LEVEL_7

0x495

AGC values level 7

(12:2) AGC_LUT_3_AGC_LEVEL_6

(12:2) AGC_LUT_3_AGC_LEVEL_6

0x485

AGC values level 6

(1:0) AGC_LUT_3_AGC_LEVEL_5_HI

(1:0) AGC_LUT_3_AGC_LEVEL_5_HI

0x2

AGC values level 5 (MSB)

0x40040C84

RF2_AGC_LUT4

(31:25) AGC_LUT_4_AGC_LEVEL_11_LO

(31:25) AGC_LUT_4_AGC_LEVEL_11_LO

0x7F

AGC values level 11 (LSB)

(24:14) AGC_LUT_4_AGC_LEVEL_10

(24:14) AGC_LUT_4_AGC_LEVEL_10

0x4FF

AGC values level 10

(13:3) AGC_LUT_4_AGC_LEVEL_9

(13:3) AGC_LUT_4_AGC_LEVEL_9

0x49F

AGC values level 9

(2:0) AGC_LUT_4_AGC_LEVEL_8_HI

(2:0) AGC_LUT_4_AGC_LEVEL_8_HI

0x4

AGC values level 8 (MSB)

0x40040C88

RF2_AGC_LUT5

(26:25) IEEE802154_OPTS_CNT_LIM_802154

(26:25) IEEE802154_OPTS_CNT_LIM_802154

0x2

Set the number of samples to wait before increasing the threshold

(24:22) IEEE802154_OPTS_CNT_OK_INC_802154

(24:22) IEEE802154_OPTS_CNT_OK_INC_802154

0x4

Set the increment to the counter that indicates that the correlators peaks are coherent

(21) IEEE802154_OPTS_USE_OS_802154

(21) IEEE802154_OPTS_USE_OS_802154

0x1

Enable the new algorithm working in the oversampled domain for the demodulation of the IEEE 802.15.4 protocol

(20) IEEE802154_OPTS_EN_DW_TEST

(20) IEEE802154_OPTS_EN_DW_TEST

0x0

Tx data-whitening before the convolutional code block

(18:16) IEEE802154_OPTS_C2B_THR

(18:16) IEEE802154_OPTS_C2B_THR

0x4

Threshold of the chip2bit correlator of the IEEE 802.15.4 protocol

(13:12) DATA_STREAMS_BER_CLK_MODE

(13:12) DATA_STREAMS_BER_CLK_MODE

0x0

Set the clock output mode for BER mode or RW mode

(10) DATA_STREAMS_RX_DATA_NOT_SAMPLED

(10) DATA_STREAMS_RX_DATA_NOT_SAMPLED

0x0

Signal rx_data in test modes sampling

(9) DATA_STREAMS_PHASE_GREY

(9) DATA_STREAMS_PHASE_GREY

0x0

Phase signal encoding

(8) DATA_STREAMS_TX_IN_CLK_TOGGLE

(8) DATA_STREAMS_TX_IN_CLK_TOGGLE

0x0

Input clock

(3:0) AGC_LUT_5_AGC_LEVEL_11_HI

(3:0) AGC_LUT_5_AGC_LEVEL_11_HI

0xE

AGC values level 11 (MSB)

0x40040C8C

RF2_AGC_ATT1

(31:30) AGC_ATT_1_AGC_ATT_AB_LO

(31:30) AGC_ATT_1_AGC_ATT_AB_LO

0x3

AGC attenuation step 10/11 (LSB)

(29:27) AGC_ATT_1_AGC_ATT_9A

(29:27) AGC_ATT_1_AGC_ATT_9A

0x5

AGC attenuation step 9/10

(26:24) AGC_ATT_1_AGC_ATT_89

(26:24) AGC_ATT_1_AGC_ATT_89

0x3

AGC attenuation step 8/9

(23:21) AGC_ATT_1_AGC_ATT_78

(23:21) AGC_ATT_1_AGC_ATT_78

0x4

AGC attenuation step 7/8

(20:18) AGC_ATT_1_AGC_ATT_67

(20:18) AGC_ATT_1_AGC_ATT_67

0x3

AGC attenuation step 6/7

(17:15) AGC_ATT_1_AGC_ATT_56

(17:15) AGC_ATT_1_AGC_ATT_56

0x2

AGC attenuation step 5/6

(14:12) AGC_ATT_1_AGC_ATT_45

(14:12) AGC_ATT_1_AGC_ATT_45

0x2

AGC attenuation step 4/5

(11:9) AGC_ATT_1_AGC_ATT_34

(11:9) AGC_ATT_1_AGC_ATT_34

0x2

AGC attenuation step 3/4

(8:6) AGC_ATT_1_AGC_ATT_23

(8:6) AGC_ATT_1_AGC_ATT_23

0x1

AGC attenuation step 2/3

(5:3) AGC_ATT_1_AGC_ATT_12

(5:3) AGC_ATT_1_AGC_ATT_12

0x1

AGC attenuation step 1/2

(2:0) AGC_ATT_1_AGC_ATT_01

(2:0) AGC_ATT_1_AGC_ATT_01

0x4

AGC attenuation step 0/1

0x40040C90

RF2_AGC_ATT2

(31:28) TIMINGS_3_T_DLL

(31:28) TIMINGS_3_T_DLL

0x2

Time needed by the DLL blocks to switch on

(27:24) TIMINGS_3_T_PLL_TX

(27:24) TIMINGS_3_T_PLL_TX

0x2

Time needed by the PLL blocks in Tx mode to switch on

(23:20) TIMINGS_2_T_SUBBAND_TX

(23:20) TIMINGS_2_T_SUBBAND_TX

0xC

Time needed by the subband algorithm to calibrate in Tx mode

(19:16) TIMINGS_2_T_TX_RF

(19:16) TIMINGS_2_T_TX_RF

0x1

Time needed by the RF blocks to switch on in Tx mode

(14:12) TIMINGS_1_T_GRANULARITY_TX

(14:12) TIMINGS_1_T_GRANULARITY_TX

0x3

Define the granularity of the timer in Tx mode

(10:8) TIMINGS_1_T_GRANULARITY_RX

(10:8) TIMINGS_1_T_GRANULARITY_RX

0x5

Define the granularity of the timer in Rx mode

(1) AGC_ATT_2_AGC_ATT_1DB

(1) AGC_ATT_2_AGC_ATT_1DB

0x0

Attenuation steps

(0) AGC_ATT_2_AGC_ATT_AB_HI

(0) AGC_ATT_2_AGC_ATT_AB_HI

0x1

AGC attenuation step 10/11 (MSB)

0x40040C94

RF2_REG25

(31) TIMEOUT_EN_RX_TIMEOUT

(31) TIMEOUT_EN_RX_TIMEOUT

0x0

Timeout of the Rx when the system is on FSM mode

(30:28) TIMEOUT_T_TIMEOUT_GR

(30:28) TIMEOUT_T_TIMEOUT_GR

0x0

Granularity of the timer in timeout Rx mode

(27:24) TIMEOUT_T_RX_TIMEOUT

(27:24) TIMEOUT_T_RX_TIMEOUT

0x0

Time that has to occur before the timeout

(21) TIMING_FAST_RX_EN_FAST_RX_TXFILT

(21) TIMING_FAST_RX_EN_FAST_RX_TXFILT

0x0

Filter Tx configuration for the fast Rx PLL

(20) TIMING_FAST_RX_EN_FAST_RX

(20) TIMING_FAST_RX_EN_FAST_RX

0x0

Fast Rx PLL

(19:16) TIMING_FAST_RX_T_RX_FAST_CHP

(19:16) TIMING_FAST_RX_T_RX_FAST_CHP

0x0

Time to switch off the fast CHP in Rx mode

(15:12) TIMINGS_5_T_RX_RF

(15:12) TIMINGS_5_T_RX_RF

0x0

Time needed by the RF blocks to switch on in Rx mode

(11:8) TIMINGS_5_T_RX_BB

(11:8) TIMINGS_5_T_RX_BB

0x1

Time needed by the BB blocks to switch on in Rx mode

(7:4) TIMINGS_4_T_SUBBAND_RX

(7:4) TIMINGS_4_T_SUBBAND_RX

0x5

Time needed by the subband algorithm to calibrate in Rx mode

(3:0) TIMINGS_4_T_PLL_RX

(3:0) TIMINGS_4_T_PLL_RX

0x1

Time needed by the PLL blocks to switch on in Rx mode

0x40040C98

RF2_BIAS_0_2

(31:28) BIAS_2_IQ_RXTX_6

(31:28) BIAS_2_IQ_RXTX_6

0x3

VCOM_MX bias

(27:24) BIAS_2_IQ_RXTX_5

(27:24) BIAS_2_IQ_RXTX_5

0x8

VCOM_LO bias

(23:20) BIAS_1_IQ_RXTX_3

(23:20) BIAS_1_IQ_RXTX_3

0x6

PrePA Casc bias

(19:16) BIAS_1_IQ_RXTX_2

(19:16) BIAS_1_IQ_RXTX_2

0x6

PrePA In bias

(15:12) BIAS_0_IQ_RXTX_1

(15:12) BIAS_0_IQ_RXTX_1

0x7

PA backoff bias

(11:8) BIAS_0_IQ_RXTX_0

(11:8) BIAS_0_IQ_RXTX_0

0x3

PA bias

(7) INTERFACE_CONF_EN_SYNC_IFACE

(7) INTERFACE_CONF_EN_SYNC_IFACE

0x0

Interfaces resynchronization

(6:4) INTERFACE_CONF_APB_WAIT_STATE

(6:4) INTERFACE_CONF_APB_WAIT_STATE

0x0

Select the number of wait states during the APB transaction

(1:0) INTERFACE_CONF_SPI_SELECT

(1:0) INTERFACE_CONF_SPI_SELECT

0x0

Select the SPI mode

0x40040C9C

RF2_BIAS_3_6

(31:28) BIAS_6_IQ_BB_0

(31:28) BIAS_6_IQ_BB_0

0x7

ACD_O bias

(27:24) BIAS_6_IQ_PLL_3

(27:24) BIAS_6_IQ_PLL_3

0x7

DLL bias

(23:20) BIAS_5_IQ_PLL_4_RX

(23:20) BIAS_5_IQ_PLL_4_RX

0x8

VCO bias for Rx mode

(19:16) BIAS_5_IQ_PLL_4_TX

(19:16) BIAS_5_IQ_PLL_4_TX

0xA

VCO bias for Tx mode

(15:12) BIAS_4_IQ_PLL_2

(15:12) BIAS_4_IQ_PLL_2

0x7

Sub-band comparator bias

(11:8) BIAS_4_IQ_PLL_1

(11:8) BIAS_4_IQ_PLL_1

0x4

Dynamic divider bias

(7:4) BIAS_3_IQ_RXTX_8

(7:4) BIAS_3_IQ_RXTX_8

0x7

IFA ctrl_c bias

(3:0) BIAS_3_IQ_RXTX_7

(3:0) BIAS_3_IQ_RXTX_7

0x7

IFA ctrl_r bias

0x40040CA0

RF2_BIAS_7_9

(31:28) BIAS_9_IQ_BB_6

(31:28) BIAS_9_IQ_BB_6

0x9

Peak detector threshold bias 0

(27:24) BIAS_9_IQ_BB_5

(27:24) BIAS_9_IQ_BB_5

0x5

Peak detector bias

(23:20) SWCAP_FSM_SB_CAP_RX

(23:20) SWCAP_FSM_SB_CAP_RX

0x0

VCO subband selection (FSM in Rx mode)

(19:16) SWCAP_FSM_SB_CAP_TX

(19:16) SWCAP_FSM_SB_CAP_TX

0x0

VCO subband selection (FSM in Tx mode)

(15:12) BIAS_8_IQ_BB_4

(15:12) BIAS_8_IQ_BB_4

0x9

RSSI_D bias

(11:8) BIAS_8_IQ_BB_3

(11:8) BIAS_8_IQ_BB_3

0xF

RSSI_G bias

(7:4) BIAS_7_IQ_BB_2

(7:4) BIAS_7_IQ_BB_2

0x6

ACD_L bias

(3:0) BIAS_7_IQ_BB_1

(3:0) BIAS_7_IQ_BB_1

0x6

ACD_C bias

0x40040CA4

RF2_BIAS_10_12

(30) SD_MASH_MASH_DITHER_TYPE

(30) SD_MASH_MASH_DITHER_TYPE

0x0

Enable the new dithering scheme

(29) SD_MASH_MASH_ENABLE

(29) SD_MASH_MASH_ENABLE

0x0

Enable the sigma delta mash

(28) SD_MASH_MASH_DITHER

(28) SD_MASH_MASH_DITHER

0x1

Enable dithering on the sigma delta mash

(27:25) SD_MASH_MASH_ORDER

(27:25) SD_MASH_MASH_ORDER

0x3

Order of the sigma delta mash

(24) SD_MASH_MASH_RSTB

(24) SD_MASH_MASH_RSTB

0x1

Reset of the sigma delta mash (active low)

(23:20) BIAS_12_LNA_AGC_BIAS_3

(23:20) BIAS_12_LNA_AGC_BIAS_3

0x6

LNA bias for AGC level 3

(19:16) BIAS_12_LNA_AGC_BIAS_2

(19:16) BIAS_12_LNA_AGC_BIAS_2

0x7

LNA bias for AGC level 2

(15:12) BIAS_11_LNA_AGC_BIAS_1

(15:12) BIAS_11_LNA_AGC_BIAS_1

0x8

LNA bias for AGC level 1

(11:8) BIAS_11_LNA_AGC_BIAS_0

(11:8) BIAS_11_LNA_AGC_BIAS_0

0x9

LNA bias for AGC level 0

(7:4) BIAS_10_IQ_BB_8

(7:4) BIAS_10_IQ_BB_8

0x0

Peak detector threshold bias 1

(3:0) BIAS_10_IQ_BB_7

(3:0) BIAS_10_IQ_BB_7

0x6

Peak detector threshold bias 2

0x40040CA8

RF2_REG2A

(27:24) SD_MASH_MASK_MASH_MASK

(27:24) SD_MASH_MASK_MASH_MASK

0x0

Mask the n LSB of the fractional part of the MASH (debug only)

(19) BIAS_EN_2_EN_PTAT

(19) BIAS_EN_2_EN_PTAT

0x1

Enable PTAT

(18:16) BIAS_EN_2_EN_BIAS_BB_HI

(18:16) BIAS_EN_2_EN_BIAS_BB_HI

0x0

Bias enable for BB (same order as biases)

(15:12) BIAS_EN_1_EN_BIAS_BB_LO

(15:12) BIAS_EN_1_EN_BIAS_BB_LO

0x0

Bias enable for BB (same order as biases)

(11:7) BIAS_EN_1_EN_BIAS_PLL

(11:7) BIAS_EN_1_EN_BIAS_PLL

0x0

Bias enable for PLL (same order as biases)

(6:0) BIAS_EN_1_EN_BIAS_RXTX

(6:0) BIAS_EN_1_EN_BIAS_RXTX

0x0

Bias enable for RxTx (same order as biases)

0x40040CAC

RF2_PLL_CTRL

(26) PLL_CTRL_DISABLE_CHP_SBS

(26) PLL_CTRL_DISABLE_CHP_SBS

0x0

Charge-pump disabling during sub-band selection (FLL and frequency ratios)

(25) PLL_CTRL_PLL_RX_48MEG

(25) PLL_CTRL_PLL_RX_48MEG

0x1

PLL frequency

(24) PLL_CTRL_SWCAP_TX_SAME_RX

(24) PLL_CTRL_SWCAP_TX_SAME_RX

0x0

Registers for Rx and Tx modes swcap in case of swcap_fsm=1

(23) PLL_CTRL_SWCAP_FSM

(23) PLL_CTRL_SWCAP_FSM

0x1

Selection of the swcap_fsm register

(22) PLL_CTRL_DLL_RSTB

(22) PLL_CTRL_DLL_RSTB

0x1

Reset signal of the DLL (active low)

(21:18) PLL_CTRL_VCO_SUBBAND_TRIM

(21:18) PLL_CTRL_VCO_SUBBAND_TRIM

0x0

VCO sub-band selection bits

(17) PLL_CTRL_SUB_SEL_OFFS_EN

(17) PLL_CTRL_SUB_SEL_OFFS_EN

0x0

Add offset to sub-band selection comparator

(16) PLL_CTRL_DIV2_CLKVCO_TEST_EN

(16) PLL_CTRL_DIV2_CLKVCO_TEST_EN

0x0

VCO signal divided by the programmable divider

(15) PLL_CTRL_VCODIV_CLK_TEST_EN

(15) PLL_CTRL_VCODIV_CLK_TEST_EN

0x0

Output on GPIO the VCO signal divided by the programmable divider

(13) PLL_CTRL_CHP_DEAD_ZONE_EN

(13) PLL_CTRL_CHP_DEAD_ZONE_EN

0x0

Charge-pump dead zone

(12:11) PLL_CTRL_CHP_CURR_OFF_TRIM_TX

(12:11) PLL_CTRL_CHP_CURR_OFF_TRIM_TX

0x3

Charge-pump offset current values selection bits in Tx mode

(10:9) PLL_CTRL_CHP_CURR_OFF_TRIM_RX

(10:9) PLL_CTRL_CHP_CURR_OFF_TRIM_RX

0x3

Charge-pump offset current values selection bits in Rx mode

(8) PLL_CTRL_HIGH_BW_FILTER_EN_TX

(8) PLL_CTRL_HIGH_BW_FILTER_EN_TX

0x1

PLL filter high bandwidth needed in Tx mode

(7) PLL_CTRL_HIGH_BW_FILTER_EN_RX

(7) PLL_CTRL_HIGH_BW_FILTER_EN_RX

0x0

PLL filter high bandwidth needed in Rx mode

(6) PLL_CTRL_FAST_CHP_EN_TX

(6) PLL_CTRL_FAST_CHP_EN_TX

0x1

High current output of the charge-pump for PLL Tx high bandwidth mode

(5) PLL_CTRL_FAST_CHP_EN_RX

(5) PLL_CTRL_FAST_CHP_EN_RX

0x0

High current output of the charge-pump for PLL Rx high bandwidth mode

(4:3) PLL_CTRL_CHP_MODE_TRIM

(4:3) PLL_CTRL_CHP_MODE_TRIM

0x0

Select the frequency inside sub-band selection

(2) PLL_CTRL_CHP_CMC_EN

(2) PLL_CTRL_CHP_CMC_EN

0x1

Common mode control block of the charge-pump

(1) PLL_CTRL_CHP_CURR_OFF_EN_TX

(1) PLL_CTRL_CHP_CURR_OFF_EN_TX

0x1

Charge-pump offset current in Tx mode

(0) PLL_CTRL_CHP_CURR_OFF_EN_RX

(0) PLL_CTRL_CHP_CURR_OFF_EN_RX

0x0

Charge-pump offset current in Rx mode

0x40040CB0

RF2_DLL_CTRL

(31:29) RSSI_TUN_1_RSSI_TUN_GAIN

(31:29) RSSI_TUN_1_RSSI_TUN_GAIN

0x1

RSSI tuning for gain

(28:24) RSSI_TUN_1_RSSI_ODD_OFFSET

(28:24) RSSI_TUN_1_RSSI_ODD_OFFSET

0x4

RSSI tuning for odd stages (offset to the even triangular wave)

(23:20) RSSI_TUN_1_RSSI_EVEN_MAX

(23:20) RSSI_TUN_1_RSSI_EVEN_MAX

0x1

RSSI tuning for even stages (maximum value of the triangular wave)

(19:16) RSSI_TUN_1_RSSI_EVEN_MIN

(19:16) RSSI_TUN_1_RSSI_EVEN_MIN

0x1

RSSI tuning for even stages (minimum value of the triangular wave)

(12) DLL_CTRL_CK_LAST_SEL_DELAY

(12) DLL_CTRL_CK_LAST_SEL_DELAY

0x0

Last SEL delay

(11) DLL_CTRL_CK_FIRST_SEL_DELAY

(11) DLL_CTRL_CK_FIRST_SEL_DELAY

0x0

First SEL delay

(10) DLL_CTRL_CK_EXT_SEL

(10) DLL_CTRL_CK_EXT_SEL

0x0

Input clock selection

(9) DLL_CTRL_CK_DIG_EN

(9) DLL_CTRL_CK_DIG_EN

0x0

Alternate ck_dig pin to output the PLL reference clock signal

(8) DLL_CTRL_CK_TEST_EN

(8) DLL_CTRL_CK_TEST_EN

0x0

Output on GPIO the PLL reference clock signal via ck_test pin

(7) DLL_CTRL_TOO_FAST_ENB

(7) DLL_CTRL_TOO_FAST_ENB

0x0

Lock range phase detector

(6) DLL_CTRL_LOCKED_DET_EN

(6) DLL_CTRL_LOCKED_DET_EN

0x1

Reference frequency multiplier locked detector

(5) DLL_CTRL_LOCKED_AUTO_CHECK_EN

(5) DLL_CTRL_LOCKED_AUTO_CHECK_EN

0x1

Frequency multiplier is out of lock (usually because some input clocks from ck_xtal or ck_ext are missing)

(4) DLL_CTRL_FAST_ENB

(4) DLL_CTRL_FAST_ENB

0x0

Disable fast mode locking of the reference frequency multiplier

(3:2) DLL_CTRL_CK_SEL_TX

(3:2) DLL_CTRL_CK_SEL_TX

0x1

Selection of the clock used as frequency reference of the PLL in Tx mode (also to ck_test and ck_dig outputs)

(1:0) DLL_CTRL_CK_SEL_RX

(1:0) DLL_CTRL_CK_SEL_RX

0x0

Selection of the clock used as frequency reference of the PLL in Rx mode (also to ck_test and ck_dig outputs)

0x40040CB4

RF2_REG2D

(29:28) PA_CONF_SW_CN

(29:28) PA_CONF_SW_CN

0x0

Harmonic 2 notch tuning

(27) PA_CONF_TX_SWITCHPA

(27) PA_CONF_TX_SWITCHPA

0x0

Switch PA

(26) PA_CONF_TX_0DBM

(26) PA_CONF_TX_0DBM

0x1

Select between PPA and PA

(25) PA_CONF_LIN_RAMP

(25) PA_CONF_LIN_RAMP

0x0

PA ramp-up linearization

(24) PA_CONF_MIN_PA_PWR

(24) PA_CONF_MIN_PA_PWR

0x1

Set the minimum power during the PA ramp-up

(23) CTRL_RX_SWITCH_LP

(23) CTRL_RX_SWITCH_LP

0x0

Switch the low-pass filter in the Rx chain

(22) CTRL_RX_USE_PEAK_DETECTOR

(22) CTRL_RX_USE_PEAK_DETECTOR

0x1

Peak detector powering

(21) CTRL_RX_START_MIX_ON_CAL

(21) CTRL_RX_START_MIX_ON_CAL

0x0

Mixer enabling

(20:16) CTRL_RX_CTRL_RX

(20:16) CTRL_RX_CTRL_RX

0xF

Rx control

(15) CTRL_ADC_PHADC_THERM_OUT_EN

(15) CTRL_ADC_PHADC_THERM_OUT_EN

0x1

Enable the buffers of phase ADC thermometric code (banked)

(14:13) CTRL_ADC_PHADC_DELLATCH

(14:13) CTRL_ADC_PHADC_DELLATCH

0x1

Phase ADC delay latch trimming (banked)

(12:8) CTRL_ADC_CTRL_ADC

(12:8) CTRL_ADC_CTRL_ADC

0x5

Phase ADC control (banked)

(6:5) RSSI_TUN_2_RSSI_TRI_CK_DIV

(6:5) RSSI_TUN_2_RSSI_TRI_CK_DIV

0x0

Speed on the RSSI triangular dithering signal (cf reg RSSI_TUN)

(4) RSSI_TUN_2_RSSI_ONE_CK_RSSI_PHADC

(4) RSSI_TUN_2_RSSI_ONE_CK_RSSI_PHADC

0x0

RSSI and phase ADC clocks sharing

(3) RSSI_TUN_2_RSSI_FULL

(3) RSSI_TUN_2_RSSI_FULL

0x1

RSSI full scale

(2) RSSI_TUN_2_RSSI_1DB

(2) RSSI_TUN_2_RSSI_1DB

0x0

LSB resolution

(1:0) RSSI_TUN_2_RSSI_PRE_ATT

(1:0) RSSI_TUN_2_RSSI_PRE_ATT

0x3

Pre attenuation of the RSSI signal

0x40040CB8

RF2_REG2E

(31:24) XTAL_TRIM_XTAL_TRIM_INIT

(31:24) XTAL_TRIM_XTAL_TRIM_INIT

0x60

Initial trimming of the XTAL

(23:16) XTAL_TRIM_XTAL_TRIM

(23:16) XTAL_TRIM_XTAL_TRIM

0x60

Trimming of the XTAL

(12) ENABLES_SEPARATE_PPA_CASC

(12) ENABLES_SEPARATE_PPA_CASC

0x0

PA cascode bit

(11:6) ENABLES_EN_RXTX

(11:6) ENABLES_EN_RXTX

0x0

Enable signals

(5:0) ENABLES_EN_BB

(5:0) ENABLES_EN_BB

0x0

Enable signals for the BB

0x40040CBC

RF2_XTAL_CTRL

(31:28) XTAL_CTRL_XO_THR_HIGH

(31:28) XTAL_CTRL_XO_THR_HIGH

0xC

High threshold for XTAL trimming

(27:24) XTAL_CTRL_XO_THR_LOW

(27:24) XTAL_CTRL_XO_THR_LOW

0x3

Low threshold for XTAL trimming

(23:22) XTAL_CTRL_XO_A_S_CURR_SEL_HIGH

(23:22) XTAL_CTRL_XO_A_S_CURR_SEL_HIGH

0x2

Value of after_startup_curr_sel when level is higher than xo_thr_high

(21:20) XTAL_CTRL_XO_A_S_CURR_SEL_LOW

(21:20) XTAL_CTRL_XO_A_S_CURR_SEL_LOW

0x0

Value of after_startup_curr_sel when level is lower than xo_thr_low

(19) XTAL_CTRL_LOW_CLK_READY_TH_EN

(19) XTAL_CTRL_LOW_CLK_READY_TH_EN

0x0

clk_ready threshold

(18) XTAL_CTRL_XTAL_CTRL_BYPASS

(18) XTAL_CTRL_XTAL_CTRL_BYPASS

0x0

Bypass the XTAL control algorithm

(17) XTAL_CTRL_DIG_CLK_IN_SEL

(17) XTAL_CTRL_DIG_CLK_IN_SEL

0x0

Clock selection for the digital block

(16) XTAL_CTRL_XO_EN_B_REG

(16) XTAL_CTRL_XO_EN_B_REG

0x1

XTAL oscillator enable

(15:14) XTAL_CTRL_XTAL_CKDIV

(15:14) XTAL_CTRL_XTAL_CKDIV

0x0

XTAL trimming speed

(13) XTAL_CTRL_CLK_OUT_EN_B

(13) XTAL_CTRL_CLK_OUT_EN_B

0x0

Output clock to go to main IP

(12) XTAL_CTRL_REG_VALUE_SEL

(12) XTAL_CTRL_REG_VALUE_SEL

0x0

Control bits of xtal_reg

(11:10) XTAL_CTRL_AFTERSTARTUP_CURR_SEL

(11:10) XTAL_CTRL_AFTERSTARTUP_CURR_SEL

0x1

Selection of the current before amplitude stabilization but after starting-up in active transistors of the core oscillator

(9:8) XTAL_CTRL_STARTUP_CURR_SEL

(9:8) XTAL_CTRL_STARTUP_CURR_SEL

0x1

Selection of the starting-up current in active transistors of the core oscillator

(7) XTAL_CTRL_INV_CLK_DIG

(7) XTAL_CTRL_INV_CLK_DIG

0x0

Invert clock on clk_dig output

(6) XTAL_CTRL_INV_CLK_PLL

(6) XTAL_CTRL_INV_CLK_PLL

0x0

Invert clock on clk_pll output

(5) XTAL_CTRL_FORCE_CLK_READY

(5) XTAL_CTRL_FORCE_CLK_READY

0x0

Force output clocks on clk_pll, clk_dig and clk_out

(4) XTAL_CTRL_CLK_DIG_EN_B

(4) XTAL_CTRL_CLK_DIG_EN_B

0x0

Disable the output clock to go to digital (clk_dig output stay low)

(3) XTAL_CTRL_BUFF_EN_B

(3) XTAL_CTRL_BUFF_EN_B

0x0

XTAL buffer disabling

(2) XTAL_CTRL_HP_MODE

(2) XTAL_CTRL_HP_MODE

0x0

Bias current increase in the clock buffer

(1) XTAL_CTRL_LP_MODE

(1) XTAL_CTRL_LP_MODE

0x0

Bias current decrease in the clock buffer

(0) XTAL_CTRL_EXT_CLK_MODE

(0) XTAL_CTRL_EXT_CLK_MODE

0x0

Use XTAL pads as external clock input

0x40040CC0

RF2_SUBBAND

(31:24) SUBBAND_OFFSET_SB_OFFSET_RX

(31:24) SUBBAND_OFFSET_SB_OFFSET_RX

0xF1

Offset to add in frequency count in order to compensate the offset of the varicap

(23:16) SUBBAND_OFFSET_SB_OFFSET

(23:16) SUBBAND_OFFSET_SB_OFFSET

0xD0

Offset to add in frequency count in order to compensate the offset of the varicap

(15:12) SWCAP_LIM_SB_MAX_VAL

(15:12) SWCAP_LIM_SB_MAX_VAL

0xF

Maximum subband value in linear search subband (freq and comp)

(11:8) SWCAP_LIM_SB_MIN_VAL

(11:8) SWCAP_LIM_SB_MIN_VAL

0x0

Minimum subband value in linear search subband (freq and comp)

(7) SUBBAND_CONF_SB_FLL_MODE

(7) SUBBAND_CONF_SB_FLL_MODE

0x1

FLL mode for the subband selection

(6) SUBBAND_CONF_SB_INV_BAND

(6) SUBBAND_CONF_SB_INV_BAND

0x0

Invert the meaning of sb_high and sb_low

(5:4) SUBBAND_CONF_SB_FREQ_CNT

(5:4) SUBBAND_CONF_SB_FREQ_CNT

0x0

The length to count in frequency mode

(3:2) SUBBAND_CONF_SB_WAIT_T

(3:2) SUBBAND_CONF_SB_WAIT_T

0x0

Time to wait to the PLL to settle

(1:0) SUBBAND_CONF_SB_MODE

(1:0) SUBBAND_CONF_SB_MODE

0x0

Sub-band algorithm mode

0x40040CC4

RF2_REG31

(31:30) RSSI_DETECT_RSSI_DET_CR_LEN

(31:30) RSSI_DETECT_RSSI_DET_CR_LEN

0x0

Number of samples to estimate the carrier offset (banked)

(29:28) RSSI_DETECT_RSSI_DET_WAIT

(29:28) RSSI_DETECT_RSSI_DET_WAIT

0x0

Symbols to wait after the RSSI detection (banked)

(27:26) RSSI_DETECT_RSSI_DET_DIFF_LL

(27:26) RSSI_DETECT_RSSI_DET_DIFF_LL

0x0

Set the distance between the actual value and the subtracted one (banked)

(25) RSSI_DETECT_EN_ABS_RSSI_DETECT

(25) RSSI_DETECT_EN_ABS_RSSI_DETECT

0x0

Absolute RSSI detection (banked)

(24) RSSI_DETECT_EN_DIFF_RSSI_DETECT

(24) RSSI_DETECT_EN_DIFF_RSSI_DETECT

0x0

Differential RSSI detection (banked)

(23) SUBBAND_CORR_SUBBAND_CORR_EN

(23) SUBBAND_CORR_SUBBAND_CORR_EN

0x0

Subband correction

(22:20) SUBBAND_CORR_SUBBAND_CORR_RX

(22:20) SUBBAND_CORR_SUBBAND_CORR_RX

0x0

Subband correction in Rx

(18:16) SUBBAND_CORR_SUBBAND_CORR_TX

(18:16) SUBBAND_CORR_SUBBAND_CORR_TX

0x0

Subband correction in Tx

(11) TXRX_CONF_INV_CLK_PLL_TX

(11) TXRX_CONF_INV_CLK_PLL_TX

0x0

Invert PLL clock when the radio is in Tx mode

(10) TXRX_CONF_INV_CLK_DIG_TX

(10) TXRX_CONF_INV_CLK_DIG_TX

0x0

Invert digital clock when the radio is in Tx mode

(9:8) TXRX_CONF_SB_WAIT_T_TX

(9:8) TXRX_CONF_SB_WAIT_T_TX

0x0

Xor value to apply to sb_wait_t (register SUBBAND_CONF) when the radio is in Tx mode

(7) PA_RAMPUP_FULL_PA_RAMPUP

(7) PA_RAMPUP_FULL_PA_RAMPUP

0x1

PA rampup configuration

(6:4) PA_RAMPUP_DEL_PA_RAMPUP

(6:4) PA_RAMPUP_DEL_PA_RAMPUP

0x4

Time to wait to start the ramp-up after the PA enable is detected

(3:2) PA_RAMPUP_TAU_PA_RAMPUP

(3:2) PA_RAMPUP_TAU_PA_RAMPUP

0x0

Time constant of the ramp-up/ramp-down

(1) PA_RAMPUP_EN_PA_RAMPDOWN

(1) PA_RAMPUP_EN_PA_RAMPDOWN

0x1

PA ramp-down

(0) PA_RAMPUP_EN_PA_RAMPUP

(0) PA_RAMPUP_EN_PA_RAMPUP

0x1

PA ramp-up linearization

0x40040CC8

RF2_DEMOD_CTRL

(31) SYNC_WORD_CORR_EN_SYNC_WORD_CORR

(31) SYNC_WORD_CORR_EN_SYNC_WORD_CORR

0x1

Sync word bias correction with RSSI detection (banked)

(29:24) SYNC_WORD_CORR_SYNC_WORD_BIAS

(29:24) SYNC_WORD_CORR_SYNC_WORD_BIAS

0x8

Set the sync word bias (banked)

(23:16) RSSI_DETECT_ABS_THR_RSSI_DET_ABS_THR

(23:16) RSSI_DETECT_ABS_THR_RSSI_DET_ABS_THR

0x0

Threshold used for absolute RSSI detection

(15:8) RSSI_DETECT_DIFF_THR_RSSI_DET_DIFF_THR

(15:8) RSSI_DETECT_DIFF_THR_RSSI_DET_DIFF_THR

0x0

Threshold used for differential RSSI detection

(7) DEMOD_CTRL_DL_SYNC_NO_DATA

(7) DEMOD_CTRL_DL_SYNC_NO_DATA

0x1

No data going through the demodulator, until the delay line detects the sync word (banked)

(6) DEMOD_CTRL_EN_DELLINE_SYNC_DET

(6) DEMOD_CTRL_EN_DELLINE_SYNC_DET

0x1

Sync word detection in the delay line (banked)

(5) DEMOD_CTRL_RSSI_DET_FILT

(5) DEMOD_CTRL_RSSI_DET_FILT

0x0

Additional filtering on the RSSI value (banked)

(4) DEMOD_CTRL_EN_FAST_CLK_RECOV

(4) DEMOD_CTRL_EN_FAST_CLK_RECOV

0x0

Clock recovery during the resto of the preamble (banked)

(3) DEMOD_CTRL_EN_MIN_MAX_MF

(3) DEMOD_CTRL_EN_MIN_MAX_MF

0x0

Min max algo after the matched filter (banked)

(2) DEMOD_CTRL_EN_PRE_SYNC

(2) DEMOD_CTRL_EN_PRE_SYNC

0x0

Sync detection on the non-delayed path (banked)

(1) DEMOD_CTRL_BLOCK_RSSI_DET

(1) DEMOD_CTRL_BLOCK_RSSI_DET

0x0

RSSI detection during the slow-down period (banked)

(0) DEMOD_CTRL_EARLY_FINE_RECOV

(0) DEMOD_CTRL_EARLY_FINE_RECOV

0x0

Early fine recovery after the packet detection or pre-sync (banked)

0x40040CCC

RF2_REG33

(26:24) CK_DIV_1_6_CK_DIV_1_6

(26:24) CK_DIV_1_6_CK_DIV_1_6

0x0

Clock division factor for ck_div_1_6

(23:16) SPARES_SPARES

(23:16) SPARES_SPARES

0x0

Spare bits

(14) PADS_PE_DS_GPIO_DS

(14) PADS_PE_DS_GPIO_DS

0x0

Increased drive strength of the digital pads

(13) PADS_PE_DS_GPIO_PE

(13) PADS_PE_DS_GPIO_PE

0x0

Pull-up of the GPIO pads

(12) PADS_PE_DS_NRESET_PE

(12) PADS_PE_DS_NRESET_PE

0x0

Pull-up of the NRESET pads

(11) PADS_PE_DS_SPI_MISO_PE

(11) PADS_PE_DS_SPI_MISO_PE

0x0

Pull-up of the SPI MISO pads

(10) PADS_PE_DS_SPI_MOSI_PE

(10) PADS_PE_DS_SPI_MOSI_PE

0x0

Pull-up of the SPI MOSI pads

(9) PADS_PE_DS_SPI_SCLK_PE

(9) PADS_PE_DS_SPI_SCLK_PE

0x0

Pull-up of the SPI CLK pads

(8) PADS_PE_DS_SPI_CS_N_PE

(8) PADS_PE_DS_SPI_CS_N_PE

0x0

Pull-up of the SPI CSN pads

(7:6) SUBBAND_FLL_SB_FLL_DITHER

(7:6) SUBBAND_FLL_SB_FLL_DITHER

0x0

Select the dithering

(5:4) SUBBAND_FLL_SB_FLL_CIC_TAU

(5:4) SUBBAND_FLL_SB_FLL_CIC_TAU

0x3

Set the CIC decimator factor

(3) SUBBAND_FLL_SB_FLL_PH_4_N8

(3) SUBBAND_FLL_SB_FLL_PH_4_N8

0x0

Phases in the frequency detector

(2:0) SUBBAND_FLL_SB_FLL_WAIT

(2:0) SUBBAND_FLL_SB_FLL_WAIT

0x3

Set the number of CIC samples before stopping the FLL

0x40040CD0

RF2_REG34

(29:24) CLK_RECOVERY_CLK_RECOV_CORR

(29:24) CLK_RECOVERY_CLK_RECOV_CORR

0x4

Number of samples that covers the clock recovery correlator

(23:16) CLK_RECOVERY_CLK_AB_LIMIT

(23:16) CLK_RECOVERY_CLK_AB_LIMIT

0x80

Time constant for switch the clock phase if chosen wrong in clk recovery algorithm

(15) TX_PRE_DIST_EN_PRE_DIST

(15) TX_PRE_DIST_EN_PRE_DIST

0x1

Tx pre-distortion filter (banked)

(13:8) TX_PRE_DIST_PRE_DIST_B0

(13:8) TX_PRE_DIST_PRE_DIST_B0

0x2E

Coefficient b0 of the Tx pre-distortion filter (banked)

(5:0) TX_PRE_DIST_PRE_DIST_A0

(5:0) TX_PRE_DIST_PRE_DIST_A0

0x2F

Coefficient a0 of the Tx pre-distortion filter (banked)

0x40040CD4

RF2_BLE_LR

(30:24) BLR_SYNC_THRESHOLD_BLE_SYNC_THR

(30:24) BLR_SYNC_THRESHOLD_BLE_SYNC_THR

0x38

Threshold for the BLR sync word detector

(19:16) BLR_PREAMBLE_BLE_PRE_THR

(19:16) BLR_PREAMBLE_BLE_PRE_THR

0x1

Threshold for the BLR preamble detector

(15) BLE_LONG_RANGE_BLR_PUT_RI_FIFO

(15) BLE_LONG_RANGE_BLR_PUT_RI_FIFO

0x1

During the reception the RI (rate indicator) is put into the Rx FIFO (banked)

(14) BLE_LONG_RANGE_BLR500_NO_ROUGH

(14) BLE_LONG_RANGE_BLR500_NO_ROUGH

0x1

Rough recovery is stopped during the 500kbps payloads of BLR packets (banked)

(13) BLE_LONG_RANGE_BLR_LIN_FILTER

(13) BLE_LONG_RANGE_BLR_LIN_FILTER

0x1

Matched filter (banked)

(12) BLE_LONG_RANGE_EN_BLR_FLUSH

(12) BLE_LONG_RANGE_EN_BLR_FLUSH

0x1

Viterbi path 0 flushing at the end of the packet (banked)

(11) BLE_LONG_RANGE_BLR_USE_EXT_LEN

(11) BLE_LONG_RANGE_BLR_USE_EXT_LEN

0x0

BLR_PKT_LEN for flushing out the Viterbi (banked)

(10) BLE_LONG_RANGE_DISABLE_BLR_TX

(10) BLE_LONG_RANGE_DISABLE_BLR_TX

0x0

Long Range feature in Tx mode (banked)

(9) BLE_LONG_RANGE_BLR_500_N125

(9) BLE_LONG_RANGE_BLR_500_N125

0x0

Data rate selection (banked)

(8) BLE_LONG_RANGE_EN_BLR

(8) BLE_LONG_RANGE_EN_BLR

0x0

BLE long range mode (banked)

(4) HW_TRIGGER_HW_TRIG_GPIO

(4) HW_TRIGGER_HW_TRIG_GPIO

0x0

HW trigger is mapped on the GPIO instead of the Tx_on signal 0x0

(3) HW_TRIGGER_HW_TRIG_SUBBAND

(3) HW_TRIGGER_HW_TRIG_SUBBAND

0x0

Activate the sub-band selection during the Tx activation

(2) HW_TRIGGER_HW_TRIG_TX_NRX

(2) HW_TRIGGER_HW_TRIG_TX_NRX

0x0

Activate the Tx mode

(1) HW_TRIGGER_HW_TRIG_LOW

(1) HW_TRIGGER_HW_TRIG_LOW

0x0

Set the trigger polarity

(0) HW_TRIGGER_HW_TRIG_ACTIVE

(0) HW_TRIGGER_HW_TRIG_ACTIVE

0x0

Enable HW trigger

0x40040CD8

RF2_REG36

(30:28) IQ_SPARES_EN_BIAS_SPARE

(30:28) IQ_SPARES_EN_BIAS_SPARE

0x0

Enable for IQ spares

(27:24) IQ_SPARES_IQ_SPARE_2

(27:24) IQ_SPARES_IQ_SPARE_2

0x0

Spare bias 2

(23:20) IQ_SPARES_IQ_SPARE_1

(23:20) IQ_SPARES_IQ_SPARE_1

0x0

Spare bias 1

(19:16) IQ_SPARES_IQ_SPARE_0

(19:16) IQ_SPARES_IQ_SPARE_0

0x0

Spare bias 0

(8) MISC_ISO_VDDA

(8) MISC_ISO_VDDA

0x0

Isolate VDDA signals

(5) BLR_DEMAPPER_BLR_SEND_DECODED_RI

(5) BLR_DEMAPPER_BLR_SEND_DECODED_RI

0x0

Fully decode the rate indicator

(4) BLR_DEMAPPER_BLR_USE_EXT_VIT_GFSK

(4) BLR_DEMAPPER_BLR_USE_EXT_VIT_GFSK

0x1

500kbps BLR uses the Viterbi GFSK decision

(3:2) BLR_DEMAPPER_BLR_500_DPHASE

(3:2) BLR_DEMAPPER_BLR_500_DPHASE

0x3

Set the distance between samples for the phase to frequency conversion in S2 mode

(1) BLR_DEMAPPER_BLR_500_LOW_GAIN

(1) BLR_DEMAPPER_BLR_500_LOW_GAIN

0x0

Set the low gain in S2 mode

(0) BLR_DEMAPPER_BLR_125_LOW_GAIN

(0) BLR_DEMAPPER_BLR_125_LOW_GAIN

0x0

Set the low gain in S8 mode

0x40040CDC

RF2_PROT_TIMER

(31) PROT_TIMER_CONF_EN_PROT_TIMER

(31) PROT_TIMER_CONF_EN_PROT_TIMER

0x0

Enable the protocol timer

(29:27) PROT_TIMER_CONF_PT_T_STP_1

(29:27) PROT_TIMER_CONF_PT_T_STP_1

0x0

Configure the time stamp 1

(26:24) PROT_TIMER_CONF_PT_T_STP_0

(26:24) PROT_TIMER_CONF_PT_T_STP_0

0x0

Configure the time stamp 0

(22) STAGING_PS_NZ_START_BIT

(22) STAGING_PS_NZ_START_BIT

0x0

Select the frequency offset

(21) STAGING_PS_NZ_START

(21) STAGING_PS_NZ_START

0x0

Start the pulse shaper with a +/- 250 kHz frequency offset

(20) STAGING_DEL_PA_RAMPDW

(20) STAGING_DEL_PA_RAMPDW

0x0

Delay the PA ramp-down by 4.5 us

(19) STAGING_PEAK_DET_TH_SHIFT

(19) STAGING_PEAK_DET_TH_SHIFT

0x0

Peak detector threshold shift

(18:17) STAGING_AGC_DERIV_LVL

(18:17) STAGING_AGC_DERIV_LVL

0x2

Select the AGC derivative level

(16) STAGING_AGC_USE_DERIV

(16) STAGING_AGC_USE_DERIV

0x0

AGC algorithm uses the derivative information to accelerate the AGC settling

(15:8) BLE_DTM_BLE_DTM_LEN

(15:8) BLE_DTM_BLE_DTM_LEN

0x25

Set the BLE DTM packet length

(7) BLE_DTM_EN_BLE_DTM

(7) BLE_DTM_EN_BLE_DTM

0x0

Enable the BLE DTM automatic packets

(3:0) BLE_DTM_BLE_DTM_PKT_TYPE

(3:0) BLE_DTM_BLE_DTM_PKT_TYPE

0x0

Set the BLE DTM packet type (see Bluetooth specification)

0x40040CE0

RF2_CTE_OPTS

(29) CTE_OPTS_RECT_PS_CTE

(29) CTE_OPTS_RECT_PS_CTE

0x0

Use rectangular pulse shape during the CTE

(28) CTE_OPTS_USE_CTE_WO_CP

(28) CTE_OPTS_USE_CTE_WO_CP

0x0

Enable the CTE without reading or inserting the CP

(27) CTE_OPTS_CTE_AMPL

(27) CTE_OPTS_CTE_AMPL

0x0

Enable the usage of the RSSI values to adapt the amplitude of the IQ signal based to the RSSI value

(26) CTE_OPTS_DF_AOA_SLOT_TIME

(26) CTE_OPTS_DF_AOA_SLOT_TIME

0x0

Indicate the switching/sampling slot period for AoA

(25) CTE_OPTS_CP_INSERT

(25) CTE_OPTS_CP_INSERT

0x0

Force the CP bit in the packet header to 1

(24) CTE_OPTS_EN_READ_CP

(24) CTE_OPTS_EN_READ_CP

0x0

CP bit is read in the packet header (BLE standard)

(23:16) CTE_OPTS_CTE_INFO

(23:16) CTE_OPTS_CTE_INFO

0x0

Set the CTEInfo field in the packet header while cp_insert is set to 1

(14:10) ASK_MOD_ASK_MAX

(14:10) ASK_MOD_ASK_MAX

0xC

Set the maximum value for the ASK modulation

(9:5) ASK_MOD_ASK_MIN

(9:5) ASK_MOD_ASK_MIN

0x0

Set the minimum value for the ASK modulation

(4:1) ASK_MOD_ASK_CNT

(4:1) ASK_MOD_ASK_CNT

0x7

Set the how long to count for the ASK modulation

(0) ASK_MOD_EN_RSSI_ASK

(0) ASK_MOD_EN_RSSI_ASK

0x0

PA will perform an ASK modulation

0x40040CE4

RF2_PT_DELTA_0

(31:30) PT_DELTA_TS_0_PT_DELTA_T0_MULT

(31:30) PT_DELTA_TS_0_PT_DELTA_T0_MULT

0x0

Multiplier for the delta t0

(19:0) PT_DELTA_TS_0_PT_DELTA_T0

(19:0) PT_DELTA_TS_0_PT_DELTA_T0

0x0

Delta t0 for the protocol timer

0x40040CE8

RF2_PT_DELTA_1

(31:30) PT_DELTA_TS_1_PT_DELTA_T1_MULT

(31:30) PT_DELTA_TS_1_PT_DELTA_T1_MULT

0x0

Multiplier for the delta t1

(19:0) PT_DELTA_TS_1_PT_DELTA_T1

(19:0) PT_DELTA_TS_1_PT_DELTA_T1

0x0

Delta t1 for the protocol timer

0x40040CEC

RF2_CTE_IF

(25:16) CTE_CTRL_DELAY_TX_DF_DELAY_TX

(25:16) CTE_CTRL_DELAY_TX_DF_DELAY_TX

0x0

Delay (in 62.5ns) form the serializer up to the antenna in direction finding (banked)

(15) ANTENNA_CONF_DF_IND_PATTERN

(15) ANTENNA_CONF_DF_IND_PATTERN

0x0

Separate the antenna switching pattern from the reference one

(14) ANTENNA_CONF_DF_IND_ANTENNA

(14) ANTENNA_CONF_DF_IND_ANTENNA

0x0

Make the antenna for DF independent from the rest of the packet

(13:8) ANTENNA_CONF_ANT_LUT_M

(13:8) ANTENNA_CONF_ANT_LUT_M

0x0

Number of states used (-1) in the antenna LUT

(5) CTE_AUTO_PULL_EXT_IQ_SMP_TYPE

(5) CTE_AUTO_PULL_EXT_IQ_SMP_TYPE

0x0

Select the external IQ sample signal qualifier type

(4) CTE_AUTO_PULL_IQ_MSB

(4) CTE_AUTO_PULL_IQ_MSB

0x0

Select which signal is sent over the MSB in case of a 16bits buffers

(3:2) CTE_AUTO_PULL_IQ_DATA_BUS_SIZE

(3:2) CTE_AUTO_PULL_IQ_DATA_BUS_SIZE

0x0

Select the bus data size of IQ signals

(1) CTE_AUTO_PULL_CTE_QUAL

(1) CTE_AUTO_PULL_CTE_QUAL

0x0

Select the CTE data qualifier

(0) CTE_AUTO_PULL_EN_CTE_AUTO_PULL

(0) CTE_AUTO_PULL_EN_CTE_AUTO_PULL

0x0

Enable the automatic push of CTE data to an external IP

0x40040CF0

RF2_CTE_CTRL

(25:16) CTE_CTRL_DELAY_RX_DF_DELAY_SWITCH_RX

(25:16) CTE_CTRL_DELAY_RX_DF_DELAY_SWITCH_RX

0x0

Delay (in 62.5ns) from the antenna up to the deserializer in direction finding (banked)

(9:0) CTE_CTRL_DELAY_RX_DF_DELAY_SAMPLE_RX

(9:0) CTE_CTRL_DELAY_RX_DF_DELAY_SAMPLE_RX

0x0

Delay (in 62.5ns) from the matched filter up to the deserializer in direction finding (banked)

0x40040CF4

RF2_AGC_ADVANCED

(26:16) AGC_SWITCHES_AGC_SHORTS_LUT

(26:16) AGC_SWITCHES_AGC_SHORTS_LUT

0x0

Array of values that indicates if the highpass shorts must be set for the AGC state passage from n -> n+1

(8) DEBUG_FAKE_IQ_SAMPLES

(8) DEBUG_FAKE_IQ_SAMPLES

0x0

Generate fake IQ samples

(7:4) AGC_ADVANCED_AGC_TAU_SHORTS

(7:4) AGC_ADVANCED_AGC_TAU_SHORTS

0x0

Time constant that indicates the time that shorts must be on

(3) AGC_ADVANCED_AGC_EN_SHORT_PHADC

(3) AGC_ADVANCED_AGC_EN_SHORT_PHADC

0x0

Enable the short on the phase ADC highpass filter

(2) AGC_ADVANCED_AGC_EN_SHORT_IFA

(2) AGC_ADVANCED_AGC_EN_SHORT_IFA

0x0

Enable the short on the IFA highpass filter

(1) AGC_ADVANCED_AGC_USE_SHORTS

(1) AGC_ADVANCED_AGC_USE_SHORTS

0x0

Enable the usage of the shorts located in the BB path

(0) AGC_ADVANCED_AGC_FULL_SPEED

(0) AGC_ADVANCED_AGC_FULL_SPEED

0x0

Enable the maximum speed in AGC

0x40040CF8

RF2_DATA_STREAMING

(9) DATA_STREAMING_DMA_PHASE_TYPE

(9) DATA_STREAMING_DMA_PHASE_TYPE

0x0

Use the phase after the rescaler instead of the raw phase from phase ADC (banked)

(8) DATA_STREAMING_DMA_EN_BUS

(8) DATA_STREAMING_DMA_EN_BUS

0x0

Enable the DMA bus on the IP interface (banked)

(6) DATA_STREAMING_PERIODIC_SAMPLE_AFTER_CTE

(6) DATA_STREAMING_PERIODIC_SAMPLE_AFTER_CTE

0x1

Restart sampling after the CTE period (banked)

(5) DATA_STREAMING_PERIODIC_SAMPLE_AT_SYNC

(5) DATA_STREAMING_PERIODIC_SAMPLE_AT_SYNC

0x0

Start sampling at the sync detection signal from the delay line (banked)

(4) DATA_STREAMING_PERIODIC_SAMPLE_OSR_CLK

(4) DATA_STREAMING_PERIODIC_SAMPLE_OSR_CLK

0x0

Oversample (8x) the reference clock of the periodic sample (banked)

(3:1) DATA_STREAMING_PERIODIC_SAMPLE_OSR

(3:1) DATA_STREAMING_PERIODIC_SAMPLE_OSR

0x3

Division factor (-1) of for the sampling period of the periodic IQ sampling (banked)

(0) DATA_STREAMING_PERIODIC_SAMPLE_EN_IQ

(0) DATA_STREAMING_PERIODIC_SAMPLE_EN_IQ

0x0

Sample periodically I and Q channels after the matched filter and put into the IQ FIFO (banked)

0x40040CFC

RF2_REVISION

-

(31:24) CHIP_ID

0x30

Remapped register of CHIP_ID

0x40040D00

RF2_FSM_CTRL

-

(31:30) RXFIFO_STATUS_RX_BIST_ERRORS

0x0

Rx FIFO BIST result

(31:25) RXFIFO_STATUS_RX_BIST

-

N/A

Start the bist test on the Rx FIFO (code 0x5d)

-

(29) RXFIFO_STATUS_RX_NEAR_UNDERFLOW

0x0

Rx FIFO near underflow

-

(28) RXFIFO_STATUS_RX_NEAR_OVERFLOW

0x0

Rx FIFO near overflow

-

(27) RXFIFO_STATUS_RX_UNDERFLOW

0x0

Rx FIFO underflow

-

(26) RXFIFO_STATUS_RX_OVERFLOW

0x0

Rx FIFO overflow

-

(25) RXFIFO_STATUS_RX_FULL

0x0

Rx FIFO full

-

(24) RXFIFO_STATUS_RX_EMPTY

0x0

Rx FIFO empty

(24) RXFIFO_STATUS_RX_FLUSH

-

N/A

Rx FIFO flush

-

(23:22) TXFIFO_STATUS_TX_BIST_ERRORS

0x0

Tx FIFO BIST result

(23:17) TXFIFO_STATUS_TX_BIST

-

N/A

Start the bist test on the Tx FIFO (code 0x5d)

-

(21) TXFIFO_STATUS_TX_NEAR_UNDERFLOW

0x0

Tx FIFO near underflow

-

(20) TXFIFO_STATUS_TX_NEAR_OVERFLOW

0x0

Tx FIFO near overflow

-

(19) TXFIFO_STATUS_TX_UNDERFLOW

0x0

Tx FIFO underflow

-

(18) TXFIFO_STATUS_TX_OVERFLOW

0x0

Tx FIFO overflow

-

(17) TXFIFO_STATUS_TX_FULL

0x0

Tx FIFO full

-

(16) TXFIFO_STATUS_TX_EMPTY

0x0

Tx FIFO empty

(16) TXFIFO_STATUS_TX_FLUSH

-

N/A

Tx FIFO flush

-

(10) FSM_STATUS_TX_NRX

0x0

Select Rx or Tx mode

-

(9:8) FSM_STATUS_STATUS

0x0

Status of the FSM

(3) FSM_MODE_RESET

-

N/A

FSM reset

-

(2) FSM_MODE_RX_MODE

0x0

Rx status

(2) FSM_MODE_TX_NRX

-

N/A

Set the radio in Tx or Rx mode

-

(1) FSM_MODE_TX_MODE

0x0

Tx status

(1:0) FSM_MODE_MODE

-

N/A

Set the FSM mode

-

(0) FSM_MODE_N_IDLE

0x0

FSM status

0x40040D04

RF2_IQFIFO_STATUS

-

(24:16) TXFIFO_COUNT_TX_COUNT

0x0

Number of bytes in the Tx FIFO

-

(15:8) IQFIFO_COUNT_IQ_COUNT

0x0

Number of bytes in the IQ FIFO

-

(7:6) IQFIFO_STATUS_IQ_BIST_ERRORS

0x0

IQ FIFO BIST result

(7:1) IQFIFO_STATUS_IQ_BIST

-

N/A

Start the BIST test on the IQ FIFO (code 0x5d)

-

(5) IQFIFO_STATUS_IQ_NEAR_UNDERFLOW

0x0

IQ FIFO near underflow

-

(4) IQFIFO_STATUS_IQ_NEAR_OVERFLOW

0x0

IQ FIFO near overflow

-

(3) IQFIFO_STATUS_IQ_UNDERFLOW

0x0

IQ FIFO underflow

-

(2) IQFIFO_STATUS_IQ_OVERFLOW

0x0

IQ FIFO overflow

-

(1) IQFIFO_STATUS_IQ_FULL

0x0

IQ FIFO full

-

(0) IQFIFO_STATUS_IQ_EMPTY

0x0

IQ FIFO empty

(0) IQFIFO_STATUS_FLUSH

-

N/A

IQ FIFO flush

0x40040D08

RF2_TXFIFO

(7:0) TXFIFO_TX_DATA

-

N/A

Data to be sent

0x40040D0C

RF2_RXFIFO

-

(7:0) RXFIFO_RX_DATA

0x0

Received data

0x40040D10

RF2_IQFIFO

-

(7:0) IQFIFO_IQ_DATA

0x0

IQ data for AoA or AoD

0x40040D14

RF2_REG45

-

(25:16) RSSI_AVG_RSSI_AVG

0x0

Filtered RSSI value

-

(8:0) RXFIFO_COUNT_RX_COUNT

0x0

Number of bytes in the Rx FIFO

0x40040D18

RF2_DESER_STATUS

-

(7) DESER_STATUS_SIGNAL_RECEIVING

0x0

Deserializer enabling

-

(6) DESER_STATUS_SYNC_DETECTED

0x0

Sync word detection

-

(5) DESER_STATUS_WAIT_SYNC

0x0

Deserializer waiting for the sync word

-

(4) DESER_STATUS_IS_ADDRESS_BR

0x0

Received address

-

(3) DESER_STATUS_PKT_LEN_ERR

0x0

Packet length

-

(2) DESER_STATUS_ADDRESS_ERR

0x0

Address error

-

(1) DESER_STATUS_CRC_ERR

0x0

CRC error

-

(0) DESER_STATUS_DESER_FINISH

0x0

Deserializer status

0x40040D1C

RF2_BLE_AEC_CCM

-

(2) BLE_AES_CCM_BLE_AES_MIC_OK

0x0

AES CCM MIC error

-

(1) BLE_AES_CCM_BLE_AES_DONE_RX

0x0

AES CCM packet decoding

-

(0) BLE_AES_CCM_BLE_AES_DONE_TX

0x0

AES CCM packet encoding

0x40040D20

RF2_IRQ_STATUS

-

(5) IRQ_STATUS_FLAG_RXFIFO

0x0

IRQ RXFIFO status

-

(4) IRQ_STATUS_FLAG_TXFIFO

0x0

IRQ TXFIFO status

-

(3) IRQ_STATUS_FLAG_SYNC

0x0

IRQ SYNC status

-

(2) IRQ_STATUS_FLAG_RECEIVED

0x0

IRQ RECEIVED status

-

(1) IRQ_STATUS_FLAG_RXSTOP

0x0

IRQ RXSTOP status

-

(0) IRQ_STATUS_FLAG_TX

0x0

IRQ Tx status

0x40040D24

RF2_RSSI_MIN_MAX

-

(25:16) RSSI_MAX_RSSI_MAX

0x0

Maximum RSSI value over a filtering period

-

(9:0) RSSI_MIN_RSSI_MIN

0x0

Minimum RSSI value over a filtering period

0x40040D28

RF2_REG4A

-

(30:28) RX_ATT_LEVEL_RX_ATT_LEVEL_PKT_LVL

0x0

Rx attenuation level (AGC level) during the packet reception

-

(26:24) RX_ATT_LEVEL_RX_ATT_LEVEL

0x0

Rx attenuation level (AGC level)

-

(23:16) DR_ERR_IND_DR_ERR_IND

0x0

Data-rate error indicator

-

(9:0) RSSI_PKT_RSSI_PKT

0x0

Filtered RSSI value sampled during the packet reception

0x40040D2C

RF2_FEI

-

(31:16) FEI_PKT_FEI_PKT

0x0

Frequency error indicator sampled during the packet reception

-

(15:0) FEI_FEI_OUT

0x0

Frequency error indicator

0x40040D30

RF2_REG4C

-

(31:24) LINK_QUAL_PKT_LINK_QUALITY_PKT

0x0

Link quality indicator sampled during the packet reception

-

(23:16) LINK_QUAL_LINK_QUALITY

0x0

Instantaneous link quality indicator

-

(15:0) FEI_AFC_FEI_AFC

0x0

Frequency error indicator sampled during the AFC

0x40040D34

RF2_ANALOG_INFO

(25:24) BLR_READOUT_BLR_RATE

-

N/A

Bluetooth LE long range rate indicator

-

(22:20) PEAK_DET_VAL_PEAK_DET_FILT

0x0

Distance from the subband center (only available with the FLL method)

-

(18:16) PEAK_DET_VAL_PEAK_DET_RAW

0x0

Distance from the subband center (only available with the FLL method)

-

(15) ANALOG_INFO_POR_VDDA

0x0

VDDA LDO disable status

-

(14) ANALOG_INFO_PLL_UNLOCK

0x0

PLL unlock status

-

(13) ANALOG_INFO_XTAL_FINISH

0x0

XTAL algorithm status

-

(12) ANALOG_INFO_DLL_LOCKED

0x0

DLL lock status

-

(11) ANALOG_INFO_CLK_DIG_READY

0x0

Ready signal of the digital clock

-

(10) ANALOG_INFO_CLK_PLL_READY

0x0

PLL clock status

-

(9:8) ANALOG_INFO_SUBBAND

0x0

Status of the subband comparator Hi

-

(7:0) SUBBAND_ERR_SB_FLL_ERR

0x0

Distance from the subband center (only available with the FLL method)

0x40040D38

RF2_SAMPLE_RSSI

(0) SAMPLE_RSSI

-

N/A

Sample the thermometric RSSI

0x40040D3C

RF2_RSSI_THERM

-

(29:0) RSSI_THERM

0x0

Thermometric value of the RSSI

0x40040D80

RF2_LUT_ANTENNA_ARRAY_1

(31:28) LUT_ANTENNA_ARRAY_1_ANTENNA_7

(31:28) LUT_ANTENNA_ARRAY_1_ANTENNA_7

0x0

Antenna 7 specification

(27:24) LUT_ANTENNA_ARRAY_1_ANTENNA_6

(27:24) LUT_ANTENNA_ARRAY_1_ANTENNA_6

0x0

Antenna 6 specification

(23:20) LUT_ANTENNA_ARRAY_1_ANTENNA_5

(23:20) LUT_ANTENNA_ARRAY_1_ANTENNA_5

0x0

Antenna 5 specification

(19:16) LUT_ANTENNA_ARRAY_1_ANTENNA_4

(19:16) LUT_ANTENNA_ARRAY_1_ANTENNA_4

0x0

Antenna 4 specification

(15:12) LUT_ANTENNA_ARRAY_1_ANTENNA_3

(15:12) LUT_ANTENNA_ARRAY_1_ANTENNA_3

0x3

Antenna 3 specification

(11:8) LUT_ANTENNA_ARRAY_1_ANTENNA_2

(11:8) LUT_ANTENNA_ARRAY_1_ANTENNA_2

0x2

Antenna 2 specification

(7:4) LUT_ANTENNA_ARRAY_1_ANTENNA_1

(7:4) LUT_ANTENNA_ARRAY_1_ANTENNA_1

0x1

Antenna 1 specification

(3:0) LUT_ANTENNA_ARRAY_1_ANTENNA_0

(3:0) LUT_ANTENNA_ARRAY_1_ANTENNA_0

0x0

Antenna 0 specification

0x40040D84

RF2_LUT_ANTENNA_ARRAY_2

(31:28) LUT_ANTENNA_ARRAY_2_ANTENNA_15

(31:28) LUT_ANTENNA_ARRAY_2_ANTENNA_15

0x0

Antenna 15 specification

(27:24) LUT_ANTENNA_ARRAY_2_ANTENNA_14

(27:24) LUT_ANTENNA_ARRAY_2_ANTENNA_14

0x0

Antenna 14 specification

(23:20) LUT_ANTENNA_ARRAY_2_ANTENNA_13

(23:20) LUT_ANTENNA_ARRAY_2_ANTENNA_13

0x0

Antenna 13 specification

(19:16) LUT_ANTENNA_ARRAY_2_ANTENNA_12

(19:16) LUT_ANTENNA_ARRAY_2_ANTENNA_12

0x0

Antenna 12 specification

(15:12) LUT_ANTENNA_ARRAY_2_ANTENNA_11

(15:12) LUT_ANTENNA_ARRAY_2_ANTENNA_11

0x0

Antenna 11 specification

(11:8) LUT_ANTENNA_ARRAY_2_ANTENNA_10

(11:8) LUT_ANTENNA_ARRAY_2_ANTENNA_10

0x0

Antenna 10 specification

(7:4) LUT_ANTENNA_ARRAY_2_ANTENNA_9

(7:4) LUT_ANTENNA_ARRAY_2_ANTENNA_9

0x0

Antenna 9 specification

(3:0) LUT_ANTENNA_ARRAY_2_ANTENNA_8

(3:0) LUT_ANTENNA_ARRAY_2_ANTENNA_8

0x0

Antenna 8 specification

0x40040D88

RF2_LUT_ANTENNA_ARRAY_3

(31:28) LUT_ANTENNA_ARRAY_3_ANTENNA_23

(31:28) LUT_ANTENNA_ARRAY_3_ANTENNA_23

0x0

Antenna 23 specification

(27:24) LUT_ANTENNA_ARRAY_3_ANTENNA_22

(27:24) LUT_ANTENNA_ARRAY_3_ANTENNA_22

0x0

Antenna 22 specification

(23:20) LUT_ANTENNA_ARRAY_3_ANTENNA_21

(23:20) LUT_ANTENNA_ARRAY_3_ANTENNA_21

0x0

Antenna 21 specification

(19:16) LUT_ANTENNA_ARRAY_3_ANTENNA_20

(19:16) LUT_ANTENNA_ARRAY_3_ANTENNA_20

0x0

Antenna 20 specification

(15:12) LUT_ANTENNA_ARRAY_3_ANTENNA_19

(15:12) LUT_ANTENNA_ARRAY_3_ANTENNA_19

0x0

Antenna 19 specification

(11:8) LUT_ANTENNA_ARRAY_3_ANTENNA_18

(11:8) LUT_ANTENNA_ARRAY_3_ANTENNA_18

0x0

Antenna 18 specification

(7:4) LUT_ANTENNA_ARRAY_3_ANTENNA_17

(7:4) LUT_ANTENNA_ARRAY_3_ANTENNA_17

0x0

Antenna 17 specification

(3:0) LUT_ANTENNA_ARRAY_3_ANTENNA_16

(3:0) LUT_ANTENNA_ARRAY_3_ANTENNA_16

0x0

Antenna 16 specification

0x40040D8C

RF2_LUT_ANTENNA_ARRAY_4

(31:28) LUT_ANTENNA_ARRAY_4_ANTENNA_31

(31:28) LUT_ANTENNA_ARRAY_4_ANTENNA_31

0x0

Antenna 31 specification

(27:24) LUT_ANTENNA_ARRAY_4_ANTENNA_30

(27:24) LUT_ANTENNA_ARRAY_4_ANTENNA_30

0x0

Antenna 30 specification

(23:20) LUT_ANTENNA_ARRAY_4_ANTENNA_29

(23:20) LUT_ANTENNA_ARRAY_4_ANTENNA_29

0x0

Antenna 29 specification

(19:16) LUT_ANTENNA_ARRAY_4_ANTENNA_28

(19:16) LUT_ANTENNA_ARRAY_4_ANTENNA_28

0x0

Antenna 28 specification

(15:12) LUT_ANTENNA_ARRAY_4_ANTENNA_27

(15:12) LUT_ANTENNA_ARRAY_4_ANTENNA_27

0x0

Antenna 27 specification

(11:8) LUT_ANTENNA_ARRAY_4_ANTENNA_26

(11:8) LUT_ANTENNA_ARRAY_4_ANTENNA_26

0x0

Antenna 26 specification

(7:4) LUT_ANTENNA_ARRAY_4_ANTENNA_25

(7:4) LUT_ANTENNA_ARRAY_4_ANTENNA_25

0x0

Antenna 25 specification

(3:0) LUT_ANTENNA_ARRAY_4_ANTENNA_24

(3:0) LUT_ANTENNA_ARRAY_4_ANTENNA_24

0x0

Antenna 24 specification

0x40040DC0

RF2_REG50

-

(27) FEATURES_HAS_BLE_AES

0x0

Bluetooth AES block availability

-

(26) FEATURES_HAS_BLE_DF_AOA_AOD

0x1

Bluetooth Direction Finding AoA/AoD feature availability

-

(25) FEATURES_HAS_BLE_LONG_RANGE

0x1

Bluetooth long range feature availability

-

(24) FEATURES_FEATURES_AVAILABLE

0x1

Features availability

(23:16) BLR_PKT_LEN_BLR_PKT_LEN

-

N/A

Packet length of the BLR packet

(15:8) PROT_TIMER_PT_CMD

-

N/A

Protocol timer command

(0) COMMANDS_START_SUBBAND

-

N/A

Subband selection algorithm

0x40040DE0

RF2_REG51

(31:24) FSM_MODE_RM_TX

(31:24) FSM_MODE_RM_TX

0x0

Remapped register of FSM_MODE

(23:16) PA_PWR_RM

(23:16) PA_PWR_RM

0x0

Remapped register of PA_PWR

(15:8) CHANNEL_RM_TX

(15:8) CHANNEL_RM_TX

0x0

Remapped register of CHANNEL

(7:0) RATE_TX

(7:0) RATE_TX

0x0

Remapped register of BANK

0x40040DE8

RF2_REG52

(31:24) ACCESS_ADDRESS

(31:24) ACCESS_ADDRESS

0x0

Remapped register of PATTERN

(23:16) FSM_MODE_RM_RX

(23:16) FSM_MODE_RM_RX

0x0

Remapped register of FSM_MODE

(15:8) CHANNEL_RM_RX

(15:8) CHANNEL_RM_RX

0x0

Remapped register of CHANNEL

(7:0) RATE_RX

(7:0) RATE_RX

0x0

Remapped register of BANK

0x40040DF0

RF2_REG53

-

(23:16) RSSI_MAX_RM

0x0

Remapped register of RSSI_MAX

-

(15:8) RSSI_MIN_RM

0x0

Remapped register of RSSI_MIN

-

(7:0) RSSI_AVG_RM

0x0

Remapped register of RSSI_AVG

0x40040DF4

RF2_REG54

(7:0) BLR_PACKET_LEN

-

N/A

Remapped register of BLR_PACKET_LEN

0x40040DF8

RF2_REG55

-

(7:0) ITRX_FEATURES

0x0

Remapped register of ITRX_FEATURES

0x40040DFC

RF2_REG56

-

(31:24) CHIP_ID_CHIP_ID

0x30

Version of the chip

-

(23:16) MD5_REGS_MD5_REGS

0x0

MD5 calculated on the register map file

(15:8) SCAN_2_SCAN_2_PASSWORD

-

N/A

SCAN 2 key

(7:0) SCAN_1_SCAN_1_PASSWORD

-

N/A

SCAN 1 key