SPI_STATUS
Bit Field |
Read/Write |
Field Name |
Description |
---|---|---|---|
13 |
R |
BUSY |
Indicate that the reception or transmission of the data is ongoing |
12 |
R |
TX_REQ |
Indicate that TX data can be written |
11 |
R |
RX_REQ |
Indicate that RX data can be read |
10 |
R |
CS_RISE |
Indicate that CS has risen in slave mode |
9 |
R |
OVERRUN |
Indicate that an overrun has occurred when receiving data on the SPI interface |
8 |
R |
UNDERRUN |
Indicate that an underrun has occurred when transmitting data on the SPI interface |
4 |
W |
TX_REQ_SET |
Set TX_REQ status flag and clear internal TX buffer status |
2 |
W |
CS_RISE_CLEAR |
Clear the CS rise status flag |
1 |
W |
OVERRUN_CLEAR |
Clear the overrun status flag |
0 |
W |
UNDERRUN_CLEAR |
Clear the underrun status flag |
Bit Field |
Field Name |
Value Symbol |
Value Description |
Hex Value |
---|---|---|---|---|
13 |
BUSY |
SPI_IDLE |
SPI idle |
0x0* |
|
|
SPI_BUSY |
SPI busy |
0x1 |
12 |
TX_REQ |
SPI_TX_NO_REQ |
SPI TX data has already been written |
0x0 |
|
|
SPI_TX_REQ |
SPI TX data can be written |
0x1* |
11 |
RX_REQ |
SPI_RX_NO_REQ |
No new SPI RX data available |
0x0* |
|
|
SPI_RX_REQ |
New SPI RX data available |
0x1 |
10 |
CS_RISE |
SPI_CS_RISE_FALSE |
CS did not rise in slave mode |
0x0* |
|
|
SPI_CS_RISE_TRUE |
CS has risen in slave mode |
0x1 |
9 |
OVERRUN |
SPI_OVERRUN_FALSE |
No SPI input overrun detected |
0x0* |
|
|
SPI_OVERRUN_TRUE |
SPI input overrun detected |
0x1 |
8 |
UNDERRUN |
SPI_UNDERRUN_FALSE |
No SPI input underrun detected |
0x0* |
|
|
SPI_UNDERRUN_TRUE |
SPI input underrun detected |
0x1 |
4 |
TX_REQ_SET |
SPI_TX_REQ_SET |
Set the TX_REQ status flag and clear internal TX buffer status |
0x1 |
2 |
CS_RISE_CLEAR |
SPI_CS_RISE_CLEAR |
Clear the SPI CS rise status bit |
0x1 |
1 |
OVERRUN_CLEAR |
SPI_OVERRUN_CLEAR |
Clear the SPI overrun status bit |
0x1 |
0 |
UNDERRUN_CLEAR |
SPI_UNDERRUN_CLEAR |
Clear the SPI underrun status bit |
0x1 |